scispace - formally typeset
A

Angelo Visconti

Researcher at STMicroelectronics

Publications -  51
Citations -  1866

Angelo Visconti is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Non-volatile memory & Flash memory. The author has an hindex of 17, co-authored 51 publications receiving 1758 citations. Previous affiliations of Angelo Visconti include Polytechnic University of Milan.

Papers
More filters
Journal ArticleDOI

Introduction to flash memory

TL;DR: The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible and an insight into the multilevel approach, where two bits are stored in the same cell, is presented.
Journal ArticleDOI

Statistical Model for Random Telegraph Noise in Flash Memories

TL;DR: In this article, a probabilistic superposition of elementary Markov processes describing the trapping/detrapping events taking place in the cell tunnel oxide was proposed to explain the main features of the random telegraph noise threshold-voltage instability.
Journal ArticleDOI

Transient conductive path induced by a Single ion in 10 nm SiO/sub 2/ Layers

TL;DR: In this article, a semi-empirical model based on the idea that a conductive path assimilable to a resistance connects the floating gate to the substrate during the time (10/sup -14/ s) needed for electrons to escape the tunnel oxide was proposed.
Journal ArticleDOI

Analytical Model for the Electron-Injection Statistics During Programming of Nanoscale nand Flash Memories

TL;DR: In this paper, a detailed analytical modeling for the constant-current Fowler-Nordheim program operation of NAND flash memories is presented, able to describe both the average transient of the cell threshold voltage and its statistical spread due to the granular nature of the electron current flowing through the cell tunnel oxide.
Journal ArticleDOI

40-mm/sup 2/ 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory

TL;DR: This paper presents a 3-V-only 64-Mb 4-level-cell (2-b/cell) NOR-type channel-hot-electron (CHE) programmed flash memory fabricated in 0.18-/spl mu/m shallow-trench isolation CMOS technology, thereby increasing device reliability while still providing layout area optimization.