IEEE transactions on very large scale integration (VLSI) systems

Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Nanowire Electronics: From Nanoscale to Macroscale

INTERSUBBAND RELAXATION IN GaAs/Al x Ga 1-x As QUANTUM WELL STRUCTURES

Two concentration ranges of silicon doping in MBE-grown GaAs films have been investigated in some detail. In lightly doped films, with a free-electron concentration of ≈1016cm−3, low-temperature photoluminescence spectra have been analysed to develop a model to account for spectral features previously attributed to Ge and Si acceptor levels. In heavily doped films, a maximum free-electron concentration of ≈7×1018 cm−3 has been obtained, which is only rather weakly dependent on growth conditions and the nature of the arsenic species (As2 or As4). Transmission electron microscopy has shown that no significant precipitation effects occur when higher Si fluxes are used but there is evidence for autocompensation. The maximum PL intensity (300 K) is found at a lower free electron concentration then with Sn-doped films, and is more sharply peaked, but there is no evidence for an anomalous Moss-Burstein shift.

Silicon doping of MBE-grown GaAs films

Physics of Semiconductor Devices. S. M. Sze. Interscience (Wiley), New York, 1969. xvi + 814 pp., illus. $19.95

In this paper, a new design of low power, high performance Radix-4 MBW multiplier unit has been described. The low power performance has been achieved by dynamic voltage scaling. Based on CCGDI technique which reduces the switching activity and output capacitance, the proposed multiplier unit has been designed by utilizing three different low power methodologies i.e., reduction in output capacitance and switching activity along with biasing voltage reduction. In order to reduce the number of transistor and delay, here GDI based parallel adders are used in the Wallace tree counters. The multiplier has been implemented with constant threshold voltage PTM 45 nm devices technology and simulated in standard CAD tool simulator for 4, 8 and 16 bit operand multiplications. The proposed design consumes 238.98 µw average power and it has a propagation delay of 2.458 ns for 16 × 16 bit multiplications at speed 100 MBps which is 47% better in terms of power-delay-product than counter based GDI Wallace tree multiplier structure.

Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications

We have theoretically investigated velocity overshoot phenomenon for both electrons and holes in bulk wurtzite GaN at 300K using one-particle Monte-Carlo method. The Boltzmann transport equation is solved incorporating deformation potential acoustic phonon, polar optical phonon, impurity and intervalley phonon scatterings. The velocity overshoot characteristics for electrons and holes at 300K reveal that higher peak drift velocities occur for higher electric field values. The variation of drift velocity with electric field shows a negative differential resistance (NDR) effect for electrons at 300K, but the NDR effect is not observed in case of hole transport. We have found that the self-oscillating frequencies of wurtzite GaN diodes are 2.62 THz, 1.74 THz and 1.31 THz corresponding to diode lengths 0.2µm, 0.3µm and 0.4µm respectively.

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Monte-Carlo study of Velocity Overshoot and Terahertz Generation in GaN

Multisolitons in SRR‐based meta-materials in klein‐gordon lattices

The polar optical phonon (POP) scattering limited mobility in 1-DEG quantum wire of GaAs has been investigated The variation of mobility with well width for 1D GaAs quantum wire has been studied The mobility dependence on the transverse dimension of quantum wire for different values of electron energy has been also been investigated The results obtained at 300K for GaAs wire reveal that the variation is almost linear in nature

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Mobility of 1-D GaAs Quantum Wire Limited by Polar Optic Phonon Scattering

Modeling and design are carried out of an n-type dual material double gate Tunnel Field Effect Transistor (DMDGTFET) using Ge as a channel material for optimization of the low power device performance parameters like subthershold swing, total gate delay, power dissipation and (On–Off) current ratio, respectively. The energy band diagram, surface potential, and electric field are obtained for on state and off state of the device by the solution of 2D Poisson’s equation utilizing indigenously developed software. The results show that both on current, and (On–Off) current ratio are higher in TFET with Ge than Si as a channel material. In this paper, authors analytically and numerically solved 2D Poisson’s equation for the optimization of low power device performance parameters by changing the channel length from 20 to 30 nm and gate oxide thickness from 2 to 5 nm, respectively. The device performance parameters such as subthershold swing, (On–Off) current ratio, total gate delay, and power dissipation are found 15 mV/decade, 2.190 × 106, 7.8 ps and 2.44 fW at channel length 20 nm and gate oxide thickness 2 nm, respectively. Thus, dual material double gate germanium-based TFETs are promising next generation devices for ultra large scale integration as well as low power digital system.

Aniruddha Ghosal

Papers

Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications

Monte-Carlo study of Velocity Overshoot and Terahertz Generation in GaN

Multisolitons in SRR‐based meta-materials in klein‐gordon lattices

Mobility of 1-D GaAs Quantum Wire Limited by Polar Optic Phonon Scattering

A Novel Approach Dual Material Double Gate Germanium-Based TFET