The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the ‘wiring bottleneck’3–6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7–9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch–Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer. A cryogenic CMOS control chip operating at 3 K is used to demonstrate coherent control and simple algorithms on silicon qubits operating at 20 mK.

CMOS-based cryogenic control of silicon quantum circuits.

A deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical in supporting ultra-low PN frequency generation for the advanced communications and other emerging high-speed applications. Unfortunately, the current literature is either full of conflicting theories and ambiguities or too complex in mathematics, hiding the physical insights. In this brief, we comprehensively review the evolution of flicker noise upconversion theories and clarify their controversial and confusing parts. Two classes of such upconversion mechanisms in voltage-biased $LC$ -tank oscillators (nMOS-only and complementary) are specifically compared and numerically verified using a commercial simulation model of 28-nm CMOS. We identify that non-resistive terminations of both 2nd and 3rd harmonic currents contribute to oscillation waveform asymmetries that lead to the flicker noise upconversion. Further, we discuss three $1/f^{3}$ PN reduction mechanisms: waveform shaping, narrowing of conduction angle, and gate-drain phase shift.

Oscillator Flicker Phase Noise: A Tutorial

The development of quantum electronic devices operating below a few Kelvin degrees is raising the demand for cryogenic complementary metal-oxide-semiconductor electronics (CMOS) to be used as in situ classical control/readout circuitry. Having a minimal spatial separation between quantum and classical hardware is necessary to limit the electrical wiring to room temperature and the associated heat load and parasitic capacitances. Here, we report prototypical demonstrations of hybrid circuits combining silicon quantum dot devices and a classical transimpedance amplifier, which is characterized and then used to measure the current through the quantum dots. The two devices are positioned next to each other at 4.2 K to assess the use of the cryogenic transimpedance amplifier with respect to a room-temperature transimpedance amplifier. A quantum device built on the same substrate as the transimpedance amplifier is characterized down to 10 mK. The transimpedance amplifier is based on commercial 28 nm fully depleted Silicon-on-insulator (FDSOI) CMOS. It consists of a two-stage Miller-compensated operational amplifier with a 10 MΩ polysilicon feedback resistor, yielding a gain of 1.1 × 10 7 V/A. We show that the transimpedance amplifier operates at 10 mK with only 1 μW of power consumption, low enough to prevent heating. It exhibits linear response up to ±40 nA and a measurement bandwidth of 2.6 kHz, which could be extended to about 200 kHz by design optimization. The realization of custom-made electronics in FDSOI technology for cryogenic operation at any temperature will improve measurement speed and quality inside cryostats with higher bandwidth, lower noise, and higher signal-to-noise ratio.

Low-power transimpedance amplifier for cryogenic integration with quantum devices

This article presents a fully integrated Cryo-CMOS system on chip (SoC) for quantum computing. The proposed SoC integrates a radio frequency (RF) pulse modulator for qubit state manipulation, a multi-tone signal generator and a coherent receiver for qubit state readout, and 22 DACs for high-speed voltage pulsing of qubit gates. By adopting frequency division multiplexing and direct digital synthesis (DDS), the RF pulse modulator can control up to 16 qubits over a single RF line, and the readout receiver can detect the state of up to six qubits simultaneously. The proposed SoC also integrates a microcontroller for low latency on-chip signal processing and increased flexibility in implementing quantum instruction sets. A detailed analysis of qubit-state readout fidelity and the impact of finite DAC resolution on two-qubit gate fidelity is also included in this article, together with an electrical specification summary. The SoC is implemented in Intel’s 22 nm FFL fin field-effect transistor (FinFET) process, and it is characterized both at room and 4 K temperatures. The performance of each specific block is measured, with the readout characterized in a loop-back configuration. Generation of the control signals required for a full Rabi oscillation experiment is also demonstrated. This article also describes the cryogenic thermalization techniques used to integrate the SoC in the dilution refrigerator and shows temperature measurements during operation.

A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits

This letter presents a fully integrated interface circuitry with a position-based charge qubit structure implemented in 22-nm FDSOI CMOS. The quantum structure is controlled by a tiny capacitive DAC (CDAC) that occupies $3.5\times 45\,\,\mu \text{m}^{2}$ and consumes 0.27mW running at a 2-GHz system clock. The state of the quantum structure is measured by a single-electron detector that consumes 1mW (including its output driver) with an area of $40\times 25\,\,\mu \text{m}^{2}$ . The low power and miniaturized layout of these circuits pave the way for integration in a large quantum core with thousands of qubits, which is a necessity for practical quantum computers. The CDAC output noise of 12 $\mu \text{V}$ -rms is estimated through mathematical analysis while the ≤ 0.225mV-rms input referred noise of the detector is verified by measurements at 3.4 K. The functionality of the system and performance of the CDAC are verified in a loopback mode with the detector sensing the CDAC-induced electron tunneling from the floating diffusion node into the quantum structure.

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A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing

This letter presents a single-electron injection device for position-based charge qubit structures implemented in 22-nm fully depleted silicon-on-insulator CMOS. Quantum dots are implemented in local well areas separated by tunnel barriers controlled by gate terminals overlapping with a thin 5-nm undoped silicon film. Interface of the quantum structure with classical electronic circuitry is provided with single-electron transistors that feature doped wells on the classic side. A small $0.7\times 0.4\,\,\mu \text{m}^{2}$ elementary quantum core is co-located with control circuitry inside the quantum operation cell which is operating at 3.5 K and a 2-GHz clock frequency. With this apparatus, we demonstrate a single-electron injection into a quantum dot.

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A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22-nm FD-SOI

We present an RF clock distribution system for a fully integrated and scalable quantum processor core operating at 3.8 K. An external 2.4 GHz signal is guided from the generator to the flip-chip package IC through a cryogenic coaxial cable. The choice of coaxial cable and the clock routing design on the PCB and IC, minimizes path loss and coupling to the supplies, the I/O signals, and more importantly the sensitive quantum core. The clock integrity up to the quantum core is maintained and verified by the jitter measurement of 0.8 ps from a test port while all circuitry within the cryo-cooler operates within the thermal load specification of 1.5 W.

Anna Koziol

Papers

A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22-nm FD-SOI

A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing

RF Clock Distribution System for a Scalable Quantum Processor in 22-nm FDSOI Operating at 3.8 K Cryogenic Temperature