/pdf/wd-yt-brwndd-lmy-dnshgh-lwm-pzshkhy-khrdstn-brss-shkhshy-lm-1zmnwizalx.pdf

وضعیت برونداد علمی دانشگاه علوم پزشکی کردستان براساس شاخصهای علم سنجی تا پایان سال 2011 میلادی

The open-source RISC-V instruction set architecture (ISA) is gaining traction, both in industry and academia. The ISA is designed to scale from microcontrollers to server-class processors. Furthermore, openness promotes the availability of various open-source and commercial implementations. Our main contribution in this paper is a thorough power, performance, and efficiency analysis of the RISC-V ISA targeting baseline “application class” functionality, i.e., supporting the Linux OS and its application environment based on our open-source single-issue in-order implementation of the 64-bit ISA variant (RV64GC) called Ariane. Our analysis is based on a detailed power and efficiency analysis of the RISC-V ISA extracted from silicon measurements and calibrated simulation of an Ariane instance (RV64IMC) taped-out in GlobalFoundries 22FDX technology. Ariane runs at up to 1.7-GHz, achieves up to 40-Gop/sW energy efficiency, which is superior to similar cores presented in the literature. We provide insight into the interplay between functionality required for the application-class execution (e.g., virtual memory, caches, and multiple modes of privileged operation) and energy cost. We also compare Ariane with RISCY, a simpler and a slower microcontroller-class core. Our analysis confirms that supporting application-class execution implies a nonnegligible energy-efficiency loss and that compute performance is more cost-effectively boosted by instruction extensions (e.g., packed SIMD) rather than the high-frequency operation.

The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology

Wavelength-dependent pump-probe spectroscopy of micelle-suspended single-walled carbon nanotubes reveals two-component dynamics. The slow component (5-20 ps), which has not been observed previously, is resonantly enhanced whenever the pump photon energy coincides with an absorption peak and we attribute it to interband carrier recombination, whereas we interpret the always-present fast component (0.3-1.2 ps) as intraband carrier relaxation in nonresonantly excited nanotubes. The slow component decreases drastically with decreasing pH (or increasing H+ doping), especially in large-diameter tubes. This can be explained as a consequence of the disappearance of absorption peaks at high doping due to the entrance of the Fermi energy into the valence band, i.e., a 1D manifestation of the Burstein-Moss effect.

Interband Recombination Dynamics in Resonantly Excited Single-Walled Carbon Nanotubes

A new approach of probing proximity effects in porphyrin-fullerene dyads by using an axial ligand coordination controlled "tail-on" and "tail-off" binding mechanism is reported. In the newly synthesized porphyrin-fullerene dyads for this purpose, the donor-acceptor proximity is controlled either by temperature variation or by an axial ligand replacement method. In o-dichlorobenzene, 0.1 M (TBA)ClO(4), the synthesized zincporphyrin-fullerene dyads exhibit seven one-electron reversible redox reactions within the accessible potential window of the solvent and the measured electrochemical redox potentials and UV-visible absorption spectra reveal little or no ground-state interactions between the C(60) spheroid and porphyrin pi-system. The proximity effects on the photoinduced charge separation and charge recombination are probed by both steady-state and time-resolved fluorescence techniques. It is observed that in the "tail-off" form the charge-separation efficiency changes to some extent in comparison with the results obtained for the "tail-on" form, suggesting the presence of some through-space interactions between the singlet excited zinc porphyrin and the C(60) moiety in the "tail-off" form. The charge separation rates and efficiencies are evaluated from the fluorescence lifetime studies. The charge separation via the singlet excited states of zinc porphyrin in the studied dyads is also confirmed by the quick rise-decay of the anion radical of the C(60) moiety within 20 ns. Furthermore, a long-lived ion pair with lifetime of about 1000 ns is also observed in the investigated zinc porphyrin-C(60) dyads.

Probing the donor-acceptor proximity on the physicochemical properties of porphyrin-fullerene dyads: "tail-on" and "tail-off" binding approach

Singlet exciton fission (SF) is a promising strategy for increasing photovoltaic efficiency, but in order for SF to be useful in solar cells, it should take place in a chromophore that is air-stable, highly absorptive, solution processable, and inexpensive. Unlike many SF chromophores, diketopyrrolopyrrole (DPP) conforms to these criteria, and here we investigate SF in DPP for the first time. SF yields in thin films of DPP derivatives, which are widely used in organic electronics and photovoltaics, are shown to depend critically on crystal morphology. Time-resolved spectroscopy of three DPP derivatives with phenyl (3,6-diphenylpyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione, PhDPP), thienyl (3,6-di(thiophen-2-yl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione, TDPP), and phenylthienyl (3,6-di(5-phenylthiophen-2-yl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione, PhTDPP) aromatic substituents in 100–200 nm thin films reveals that efficient SF occurs only in TDPP and PhTDPP (τSF = 220 ± 20 ps), despite the fact that SF is most exoergic in PhDPP. This result correlates well with the greater degree of π-overlap and closer π-stacking in TDPP (3.50 A) and PhTDPP (3.59 A) relative to PhDPP (3.90 A) and demonstrates that SF in DPP is highly sensitive to the electronic coupling between adjacent chromophores. The triplet yield in PhTDPP films is determined to be 210 ± 35% by the singlet depletion method and 165 ± 30% by the energy transfer method, showing that SF is nearly quantitative in these films and that DPP derivatives are a promising class of SF chromophores for enhancing photovoltaic performance.

Effects of Crystal Morphology on Singlet Exciton Fission in Diketopyrrolopyrrole Thin Films B

With increased usage of compute cores for sensitive applications, including e-commerce, there is a need to provide additional hardware support for securing information from memory based attacks. This work presents a unified hardware framework for handling spatial and temporal memory attacks. The paper integrates the proposed hardware framework with a RISC-V based micro-architecture with an enhanced application binary interface that enables software layers to use these features to protect sensitive data. We demonstrate the effectiveness of the proposed scheme through practical case studies in addition to taking the design through a VLSI CAD design flow. The proposed processor reduces the metadata storage overhead up to 4 x in comparison with the existing solutions, while incurring an area overhead of just 1914 LUTs and 2197 flip flops on an FPGA, without affecting the critical path delay of the processor.

Shakti-T: A RISC-V Processor with Light Weight Security Extensions

State-of-the-Art Computer Architecture research at Indian Academic Institutions is majorly restricted due to unavailability of processor design models that are close to current commercially available cores. The SHAKTI processor initiative aims at breaking this barrier between Academia and Industry by providing open-source Processor and SoC designs. With the advent of RISC-V ISA by UC Berkeley, we have a simple, clean and most importantly an open source ISA that can be used to design processors which have the potential to match the current day processors in the market. The initiative is also driven to provide substantial information about design decisions and promote more competitive learning environment in academia. The processors from SHAKTI will help in aiding research related to architecture, where one can run simulations on the actual hardware and obtain much accurate results, rather than settling with a lesser accurate software simulation. Since these processors and designs are targeted for real-world use, they can also be freely adopted by industries, thereby supporting the initiative further in terms of product-driven research.In this workshop we plan to talk about the various designs that we are working on and how they can be used. The proposed tutorial consists of four parts. The first part emphasizes on the need for open-source hardware design and the rationale behind our choices of ISA and HDL. The second part covers about our microcontroller class (C-class) core and the verification and debug environment. The third part presents our flagship processor which is the industrial class (I-class) core; the various design decisions involved and some performance metrics. The final part concludes on the note of future work and upcoming releases under SHAKTI.

SHAKTI Processors: An Open-Source Hardware Initiative

The formation of discrete macrocycles wrapped around single-walled carbon nanotubes (SWCNTs) has recently emerged as an appealing strategy to functionalize these carbon nanomaterials and modify their properties. Here, we demonstrate that the reversible disulfide exchange reaction, which proceeds under mild conditions, can install relatively large amounts of mechanically interlocked disulfide macrocycles on the one-dimensional nanotubes. Size-selective functionalization of a mixture of SWCNTs of different diameters were observed, presumably arising from error correction and the presence of relatively rigid, curved π-systems in the key building blocks. A combination of UV/Vis/NIR, Raman, photoluminescence excitation, and transient absorption spectroscopy indicated that the small (6,4)-SWCNTs were predominantly functionalized by the small macrocycles 12 , whereas the larger (6,5)-SWCNTs were an ideal match for the larger macrocycles 22 . This size selectivity, which was rationalized computationally, could prove useful for the purification of nanotube mixtures, since the disulfide macrocycles can be removed quantitatively under mild reductive conditions.

https://onlinelibrary.wiley.com/doi/pdf/10.1002/anie.202005081

Dynamic Covalent Formation of Concave Disulfide Macrocycles Mechanically Interlocked with Single-Walled Carbon Nanotubes

Here, the ability of a novel near-infrared dye to noncovalently self-assemble onto the surface of single-walled carbon nanotubes (SWCNTs) driven by charge-transfer interactions is demonstrated. Steady-state, Raman, and transient absorption spectroscopies corroborate the electron donating character of the near-infrared dye when combined with SWCNTs, in the form of fluorescence quenching of the excited state of the dye, n-doping of SWCNTs, and reversible charge transfer, respectively. Formation of the one-electron oxidized dye as a result of interactions with SWCNTs is supported by spectroelectrochemical measurements. The ultrafast electronic process in the near-infrared dye, once immobilized onto SWCNTs, starts with the formation of excited states, which decay to the ground state via the intermediate population of a fully charge-separated state, with characteristic time constants for the charge separation of 1.5 ps and charge recombination of 25 ps, as derived from the multiwavelength global analysis. Of great relevance is the fact that charge-transfer occurs from the hot excited state of the near-infrared dye to SWCNTs.

https://onlinelibrary.wiley.com/doi/epdf/10.1002/smll.201906745

Reversible Charge Transfer with Single-Walled Carbon Nanotubes Upon Harvesting the Low Energy Part of the Solar Spectrum.

In this era of IoT devices, security is very often traded off for smaller device footprint and low power consumption. Considering the exponentially growing security threats of IoT and cyber-physical systems, it is important that these devices have built-in features that enhance security. In this paper, we present Shakti-MS, a lightweight RISC-V processor with built-in support for both temporal and spatial memory protection. At run time, Shakti-MS can detect and stymie memory misuse in C and C++ programs, with minimum runtime overheads. The solution uses a novel implementation of fat-pointers to efficiently detect misuse of pointers at runtime. Our proposal is to use stack-based cookies for crafting fat-pointers instead of having object-based identifiers. We store the fat-pointer on the stack, which eliminates the use of shadow memory space, or any table to store the pointer metadata. This reduces the storage overheads by a great extent. The cookie also helps to preserve control flow of the program by ensuring that the return address never gets modified by vulnerabilities like buffer overflows. Shakti-MS introduces new instructions in the microprocessor hardware, and also a modified compiler that automatically inserts these new instructions to enable memory protection. This co-design approach is intended to reduce runtime and area overheads, and also provides an end-to-end solution. The hardware has an area overhead of 700 LUTs on a Xilinx Virtex Ultrascale FPGA and 4100 cells on an open 55nm technology node. The clock frequency of the processor is not affected by the security extensions, while there is a marginal increase in the code size by 11% with an average runtime overhead of 13%.

Arjun Menon

Papers

Shakti-T: A RISC-V Processor with Light Weight Security Extensions

SHAKTI Processors: An Open-Source Hardware Initiative

Dynamic Covalent Formation of Concave Disulfide Macrocycles Mechanically Interlocked with Single-Walled Carbon Nanotubes

Reversible Charge Transfer with Single-Walled Carbon Nanotubes Upon Harvesting the Low Energy Part of the Solar Spectrum.

SHAKTI-MS: a RISC-V processor for memory safety in C