This work proposes a power‐efficient half‐rate current‐integrating logic (CIL) echo cancelation hybrid circuit topology for full‐duplex communication for off‐chip interconnects in 65 nm CMOS. The proposed hybrid topology has a low power consumption compared to traditional current‐mode hybrid circuit topology implementations, thanks to the CIL hybrid topology with sample and hold front‐end. The post‐layout performance of the half‐rate CIL hybrid includes package parasitic has a differential received signal voltage swing of 190 mV at 10 Gb/s data rate with a timing jitter of 16 ps over a 20 cm FR4 PCB interconnect. The total power consumption of the half‐rate CIL hybrid is only 2 mW, and its energy efficiency is 0.4 pJ/bit. The layout of the hybrid occupies an area of 0.0008 mm2.

A power‐efficient current‐integrating hybrid for full‐duplex communication over chip‐to‐chip interconnects

This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed.

Wireline communication: the backbone of data transfer

In this paper, a low-power half-rate charge-steering echo cancellation hybrid circuit topology is proposed for full-duplex signaling over chip-to-chip interconnects. The proposed half-rate charge-steering hybrid topology has a very low power consumption compared to traditional current-mode and voltage-mode hybrid circuit topology implementations, thanks to the discrete nature of charge-steering hybrid topology avoiding direct current path between V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> and ground. The half-rate hybrid circuit topology has been implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout performance of the half-rate charge-steering hybrid including package parasitic has a differential received signal voltage swing of 0.8 V at 10 Gb/s data rate with a timing jitter of 10 ps over a FR4 PCB interconnect of length 20 cm. The total power consumption of the half-rate charge-steering hybrid is only 0.16 mW and its energy efficiency is 0.032 pJ/bit. The layout of the hybrid occupies an area of 0.0007 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . 

A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects

SUMMARY This paper presents a channel operating margin (COM) based high-speed serial link optimization using machine learning (ML). COM that is proposed for evaluating serial link is calculated at ﬁrst and dur- ing the calculation several important equalization parameters corresponding to the best conﬁguration are extracted which can be used for the ML modeling of serial link. Then a deep neural network containing hidden layers are investigated to model a whole serial link equalization including transmitter feed forward equalizer (FFE), receiver continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE). By training, val- idating and testing a lot of samples that meet the COM speciﬁcation of 400GAUI-8 C2C, an e ﬀ ective ML model is generated and the maximum relative error is only 0.1 compared with computation results. At last 3 link conﬁgurations are discussed from the view of tradeo ﬀ between the link per- formance and cost, illustrating that our COM based ML modeling method can be applied to advanced serial link design for NRZ, PAM4 or even other higher level pulse amplitude modulation signal.

https://www.jstage.jst.go.jp/article/transele/E105.C/11/E105.C_2021ESP0003/_pdf

A COM Based High Speed Serial Link Optimization Using Machine Learning

In this paper, an energy efficient current-mode hybrid circuit topology for echo-cancellation is proposed for full-duplex signalling over chip-to-chip interconnects. Conventional full-duplex transceivers consists of three transcondutors, namely, for transmitting the outbound signal, for replica generation and for cancellation or subtraction, leading to an increase in the power consumption. However, the proposed hybrid circuit topology consists of only two transconductors, transmitter and replica generator. The separation of the inbound signal from the signal on the line is achieved using a simple resistor, thereby eliminating the need of additional transconductor for subtraction. This makes the proposed hybrid an attractive choice for realizing power efficient full-duplex transceiver compared to the existing transceiver with current-mode and voltage-mode hybrid circuit topologies. The proposed hybrid is implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout simulation including the package parasitic has a differential received signal voltage swing of 85 mV at 10 Gb/s data rate over a 20-cm FR4 PCB trace. The total power consumption of the hybrid is 0.29 mW and the corresponding energy efficiency is 0.057 pJ/bit. The layout of the hybrid occupies an area of 0.00025 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . 

Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects

We present a full-duplex 3 Gb/s PAM4 voltage-mode transmitter with an embedded 2-tap feed forward equalizer. In full-duplex mode, the transmitter employs an echo canceller to cancel the locally transmitted signal and recover the signal from the far-end. The transmitter achieves energy proportionality with output swings and equalizer coefficients. Fabricated in 65 nm Digital CMOS process, the transmitter transmits a maximum of 1 V peak-to-peak differential output swing. In full-duplex mode, the transmitter equalizes 2 m UTP cable and dissipates 37.3 mW at 3Gb/s with echo canceller in the receiver path. The power reduces to 18.3 mW while transmitting across a 9 m UTP cable in the half-duplex mode.

Ashish Das

Papers

An Energy-Efficient 3Gb/s PAM4 Full-Duplex Transmitter With 2-Tap Feed Forward Equalizer