A semiconductor p-n junction typically has a doping-induced carrier depletion region, where the doping level positively correlates with the built-in potential and negatively correlates with the depletion layer width. In conventional bulk and atomically thin junctions, this correlation challenges the synergy of the internal field and its spatial extent in carrier generation/transport. Organic-inorganic hybrid perovskites, a class of crystalline ionic semiconductors, are promising alternatives because of their direct badgap, long diffusion length, and large dielectric constant. Here, strong depletion in a lateral p-n junction induced by local electronic doping at the surface of individual CH3 NH3 PbI3 perovskite nanosheets is reported. Unlike conventional surface doping with a weak van der Waals adsorption, covalent bonding and hydrogen bonding between a MoO3 dopant and the perovskite are theoretically predicted and experimentally verified. The strong hybridization-induced electronic coupling leads to an enhanced built-in electric field. The large electric permittivity arising from the ionic polarizability further contributes to the formation of an unusually broad depletion region up to 10 µm in the junction. Under visible optical excitation without electrical bias, the lateral diode demonstrates unprecedented photovoltaic conversion with an external quantum efficiency of 3.93% and a photodetection responsivity of 1.42 A W-1 .

Strong Depletion in Hybrid Perovskite p-n Junctions Induced by Local Electronic Doping.

This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell–Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation.

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Cryogenic MOS Transistor Model

FinFET is a multiple-gate silicon transistor structure that nowadays is attracting an extensive attention to progress further into the nanometer era by going beyond the downscaling limit of the conventional planar CMOS technology. Although the interest for this architecture has been mainly devoted to digital applications, the analysis at high frequency is crucial for targeting a successful mixed integration of analog and digital circuits. In view of that, the purpose of this review paper is to provide a clear and exhaustive understanding of the state of art, challenges, and future trends of the FinFET technology from a microwave modeling perspective. Inspired by the traditional modeling techniques for conventional MOSFETs, different strategies have been proposed over the last years to model the FinFET behavior at high frequencies. With the aim to support the development of this technology, a comparative study of the achieved results is carried out to gain both a useful feedback to investigate the microwave FinFET performance as well as a valuable modeling know-how. To accomplish a comprehensive review, all aspects of microwave modeling going from linear (also noise) to non-linear high-frequency models are addressed.

A comprehensive review on microwave FinFET modeling for progressing beyond the state of art

Nanoscale devices have great potential for providing a platform for detecting biomolecules. There are a number of difficulties observed during the fabrication process of these devices, such as random dopant fluctuation, thermal budget, and so on. To cut down these problems, charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field-effect transistor (CPB DM-JLTFET) for the label free electrical recognition of biomolecules like cell, enzyme, deoxyribonucleic acid, protein, and so on via incorporating the dielectric modulation technique. A gate underlap region is formed in the device via etching oxide material. Label free detection of biomolecules depends upon the electrical property of biomolecules. The effect of device parameters such as cavity length and cavity thickness on surface potential, subthreshold slope, $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ ratio, and their sensitivity have been discussed. This paper investigates the performance of CPB DM-JLTFET for biomolecule sensing applications while varying dielectric constant, surface density, cavity length, and cavity thickness at different biasing conditions. The device proposed is implemented and simulated by using an ATLAS device simulator.

Parametric Variation Analysis of Symmetric Double Gate Charge Plasma JLTFET for Biosensor Application

This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

For the first time, the idea of a two-dimensional p-n junction formed as a contact between two regions of a quantum-dimensional film with different types of conductivity is proposed. Under equilibrium conditions, the potential distribution and the potential-barrier height were determined. An expression was derived for the width of the surface-charge layer, which depends linearly on the contact potential (external bias) in contrast to the three-dimensional case. The specific capacitance of a two-dimensional p-n junction is virtually independent of the applied potential and depends only on the ambient permittivity. It was shown that, in spite of the fact that the junction electric field is screened only slightly, the Schottky approximation can be used for a description of the properties of such p-n junctions.

Two-dimensional p-n junction under equilibrium conditions

A physical and explicit compact model for lightly doped FinFETs is presented. This design-oriented model is valid for a large range of silicon Fin widths and lengths, using only a very few number of model parameters. The quantum mechanical effects (QMEs), which are very significant for thin Fins below 15 nm, are included in the model as a correction to the surface potential. A physics-based approach is also followed to model short-channel effects (roll-off), drain-induced barrier lowering (DIBL), subthreshold slope degradation, drain saturation voltage, velocity saturation, channel length modulation and carrier mobility degradation. The quasi-static model is then developed and accurately accounts for small-geometry effects as well. This compact model is accurate in all regions of operation, from weak to strong inversion and from linear to saturation regions. It has been implemented in the high-level language Verilog-A and exhibits an excellent numerical efficiency. Finally, comparisons of the model with 3D numerical simulations show a very good agreement making this model well-suited for advanced circuit simulations.

Physics-based compact model for ultra-scaled FinFETs

Nanowire (NW) semiconductors are interesting devices for being used as sensors. Such NWs are doped silicon channels with electrical contacts at both ends, which is a kind of the so-called junctionless (JL) device. However, in contrast with the state-of-the-art CMOS FETs, a relatively high concentration of traps is expected when using these architectures as biosensors, since their surface is supposed to be in contact with chemicals and gases. A major concern is that these traps will substantially modify the charge–voltage characteristics, thus asking for improvement of basic compact models. In this respect, we have included the effect of interface traps in NW and double-gate JL devices through a charge-based model that has been developed previously. The soundness of this approach is confirmed by extensive comparisons with numerical technology computer-aided design simulation, while the analytical formulation helps understanding the most relevant parameters of the traps with respect to the technology.

Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

This paper presents an explicit drain current model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor. Analytical relationships for the channel charge densities and for the drain current are derived as explicit functions of applied terminal voltages and structural parameters. The model is validated with 2D numerical simulations for a large range of channel thicknesses and is found to be very accurate for doping densities exceeding 10(18) cm(-3), which are actually used for such devices. (C) 2013 Elsevier Ltd. All rights reserved.

Explicit drain current model of junctionless double-gate field-effect transistors

In this article, we present a theoretical analysis of a junctionless (JL), ion-sensitive, field-effect-transistor (ISFET), self-consistently combining the electrochemical interaction between the semiconductor–insulator interface and the surrounding electrolyte medium. Incorporating charge-based core relationships for the nanowire (NW) and planar double gate (DG) JL FETs with basic relations governing the electrolyte–insulator proton exchanges, we predict the output characteristics of the NW and DG JL ISFETs with respect to pH for all the regions of operation. This hybrid charge-based approach of JL ISFETs is fully validated by COMSOL Multiphysics simulations without the need to introduce any fitting parameters. These developments are suitable for implementation in circuit simulators as well as for fast prototyping by tuning the technological parameters and estimate their impact on the device performances, including the electrolyte medium.

Ashkhen Yesayan

Papers

Two-dimensional p-n junction under equilibrium conditions

Physics-based compact model for ultra-scaled FinFETs

Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

Explicit drain current model of junctionless double-gate field-effect transistors

Analytical Modeling of Double-Gate and Nanowire Junctionless ISFETs