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Ashwin H. Shah
Researcher at Texas Instruments
Publications - 51
Citations - 1550
Ashwin H. Shah is an academic researcher from Texas Instruments. The author has contributed to research in topics: Static random-access memory & Trench. The author has an hindex of 20, co-authored 51 publications receiving 1543 citations.
Papers
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Journal ArticleDOI
Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon
Satwinder Malhi,Hisashi Shichijo,Sanjay K. Banerjee,R. Sundaresan,M. Elahy,Gordon P. Pollack,William F. Richardson,Ashwin H. Shah,L.R. Hite,R.H. Womack,Pallab K. Chatterjee,H.W. Lam +11 more
TL;DR: In this paper, a design methodology was developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools.
Patent
Vertical DRAM cell and method
TL;DR: In this paper, a method for forming DRAM cells in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during fabrication is described.
Proceedings ArticleDOI
A trench transistor cross-point DRAM cell
William F. Richardson,D.M. Bordelon,Gordon P. Pollack,Ashwin H. Shah,Satwinder Malhi,Hisashi Shichijo,Sanjay K. Banerjee,M. Elahy,R.H. Womack,Chu-Ping Wang,James D. Gallia,H.E. Davis,Pallab K. Chatterjee +12 more
TL;DR: In this article, a 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described, and its fabrication and characterization is discussed.
Patent
Dram cell and method
TL;DR: In this paper, a memory cell is constructed within a single trench, where the bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor and the substrate serves as the other plate of the capacitor.
Journal ArticleDOI
Hydrogen passivation of PolySilicon MOSFET's from a plasma Nitride source
Gordon P. Pollack,William F. Richardson,Satwinder Malhi,T.D. Bonifield,Hisashi Shichijo,Sanjay K. Banerjee,M. Elahy,Ashwin H. Shah,R.H. Womack,Pallab K. Chatterjee +9 more
TL;DR: In this article, a simple method for the "last step" passivation of grain boundaries in polysilicon MOSFET's is presented, which involves diffusion of atomic hydrogen at 450°C from a plasma-deposited compressive silicon nitride layer for reaction at silicon grain-boundary dangling bond sites.