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William F. Richardson
Researcher at Texas Instruments
Publications - 29
Citations - 1422
William F. Richardson is an academic researcher from Texas Instruments. The author has contributed to research in topics: Trench & Transistor. The author has an hindex of 19, co-authored 29 publications receiving 1401 citations.
Papers
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Journal ArticleDOI
Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon
Satwinder Malhi,Hisashi Shichijo,Sanjay K. Banerjee,R. Sundaresan,M. Elahy,Gordon P. Pollack,William F. Richardson,Ashwin H. Shah,L.R. Hite,R.H. Womack,Pallab K. Chatterjee,H.W. Lam +11 more
TL;DR: In this paper, a design methodology was developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools.
Journal ArticleDOI
A new three-terminal tunnel device
TL;DR: In this paper, a closed-form analytical model for the tunneling current in the trench transistor cell (TTC) is presented, which is used in Texas Instruments' 4-Mbit DRAM.
Proceedings ArticleDOI
A trench transistor cross-point DRAM cell
William F. Richardson,D.M. Bordelon,Gordon P. Pollack,Ashwin H. Shah,Satwinder Malhi,Hisashi Shichijo,Sanjay K. Banerjee,M. Elahy,R.H. Womack,Chu-Ping Wang,James D. Gallia,H.E. Davis,Pallab K. Chatterjee +12 more
TL;DR: In this article, a 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described, and its fabrication and characterization is discussed.
Patent
DRAM Cell with trench capacitor and vertical channel in substrate
TL;DR: In this paper, a dRAM cell and array of cells, together with a method of fabrication, was described, where the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate.
Patent
Method of making DRAM cell with trench capacitor
TL;DR: In this article, a dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate.