An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates.

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Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness

Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed.

http://userweb.eng.gla.ac.uk/andrew.brown/papers/IEEE_TED_2003_Review_Paper.pdf

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Silicon germanium (SiGe) has moved from being a research material to accounting for a small but significant percentage of manufactured semiconductor devices. This percentage is predicted to increase substantially as SiGe begins to be used in complementary metal oxide semiconductor (CMOS) technology in the future to substantially improve performance. It is the development of Si/SiGe heterostructures which has enabled band structure and strain engineering allowing Si/SiGe to be used in many different ways to improve conventional microelectronic device performance along with allowing new concepts to be explored. This paper presents a review of the material properties, growth techniques, band structure and the main electronic devices of the Si/SiGe heterostructure system. In particular, the important device technologies in mainstream microelectronics of the SiGe heterostructure bipolar transistor (HBT) and strained-Si CMOS will be reviewed before future device and optoelectronics concepts are explored.

https://iopscience.iop.org/article/10.1088/0268-1242/19/10/R02/pdf

Si/SiGe heterostructures: from material and physics to devices and circuits

A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Semiconductor transistor having a stressed channel

A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Six Ge1-x, Six Sn1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

Insulated-gate transistor having narrow-bandgap-source

Flash-lamp annealing (FLA) technology, a new method of activating implanted impurities, is proposed. FLA is able to reduce the time of the heating cycle to within the millisecond range. With this technology, an abrupt profile is realized, with a dopant concentration that can exceed the maximum carrier concentration obtained by conventional rapid thermal annealing (RTA) or furnace annealing. In contrast to a laser annealing method, FLA can activate dopants in an 8-inch-diameter substrate and, simultaneously, strictly control diffusion of dopants so as not to melt the substrate surface by radiation. FLA presents the possibility of fabricating sub-0.1-µm MOSFETs with good characteristics.

https://iopscience.iop.org/article/10.1143/JJAP.41.2394/pdf

10–15 nm Ultrashallow Junction Formation by Flash-Lamp Annealing

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

An electrically conductive mask having openings formed is located above a semiconductor substrate and ions are implanted into the surface of the semiconductor substrate through the electrically conductive mask, thereby forming ion implanted layers. For ion implantation under different conditions, a dedicated electrically conductive mask is used with each ion implantation step.

Ion implantation apparatus, ion generating apparatus and semiconductor manufacturing method with ion implantation processes

According to one embodiment, a solid-state imaging device includes a multilayer wiring layer, a semiconductor substrate, an impurity diffusion region of a second conductivity type, an anti-reflection film, a color filter, and a metallic layer. The semiconductor substrate is provided on the multilayer wiring layer and includes a first conductivity type layer. The impurity diffusion region of the second conductivity type partitions the first conductivity type layer into a plurality of regions. The anti-reflection film is provided on the semiconductor substrate. The color filter is provided on the anti-reflection film for each of the partitioned regions. The metallic layer is formed in a region of a lower surface of the semiconductor substrate except the partitioned regions. The anti-reflection film is not provided in a region immediately above the metallic layer.

Atsushi Murakoshi

Papers

Insulated-gate transistor having narrow-bandgap-source

10–15 nm Ultrashallow Junction Formation by Flash-Lamp Annealing

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

Ion implantation apparatus, ion generating apparatus and semiconductor manufacturing method with ion implantation processes

Solid-state imaging device and method for manufacturing same