A self-calibration technique based upon charge storage on the gate-source capacitance of CMOS transistors is presented. The technique can produce multiple copies of a reference current. Therefore, it is suitable for the calibration of high-resolution D/A (digital/analog) converters which are based upon equal current sources. As the storage capacitor is internal, no external components are required. A calibrated spare current source is used to allow continuous converter operation. This implies that no special calibration cycles are required. To show the capabilities of the calibration technique, it was implemented in a 16-b D/A converter. Measurement results show a total harmonic distortion of 0.0025% at a power consumption of 20 mW and a minimum supply voltage of 3 V. The design was fabricated in a 1.6- mu m double-metal CMOS process without special options. >

A self-calibration technique for monolithic high-resolution D/A converters

This paper describes new techniques for the simulation and power distribution synthesis of mixed analog/digital integrated circuits considering the parasitic coupling of noise through the common substrate. By spatially discretizing a simplified form of Maxwell's equations, a three-dimensional linear mesh model of the substrate is developed. For simulation, a macromodel of the fine substrate mesh is formulated and a modified version of SPICE3 is used to simulate the electrical circuit coupled with the macromodel. For synthesis, a coarse substrate mesh, and interconnect models are used to couple linear macromodels of circuit functional blocks. Asymptotic Waveform Evaluation (AWE) is used to evaluate the electrical behavior of the network at every iteration in the synthesis process. Macromodel simulations are significantly faster than device level simulations and compare accurately to measured results. Synthesis results demonstrate the critical need to constrain substrate noise and simultaneously optimize power bus geometry and pad assignment to meet performance targets. >

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Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis

A complete monolithic stereo 16-bit D/A converter primarily intended for use in compact-disc players and digital audio tape recorders is described. The D/A converter achieves 16-bit resolution by using a code-conversion technique based upon oversampling and noise shaping. The band-limiting filters required for waveform smoothing and out-of-band noise reduction are included. Owing to the oversampling principle most applications will require only a few components for an analog postfilter. The converter has a linear characteristic and linear phase response. The chip is processed in a 2-/spl mu/m CMOS process and the die size is 44 mm/SUP 2/. Only a single 5-V supply is needed.

A CMOS stereo 16-bit D/A converter for digital audio

High-speed high-resolution /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) for broad-band communication applications must be designed at a low oversampling ratio (OSR) However, lowering the OSR limits the efficiency of a /spl Delta//spl Sigma/ ADC in achieving a high-resolution A/D conversion This paper presents several techniques that enable the OSR reduction in /spl Delta//spl Sigma/ ADCs without compromising the resolution 1) Noise transfer function (NTF) In this paper, a single-stage multibit /spl Delta//spl Sigma/ modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-to-quantization-noise ratios at low OSRs Its key features include: decreased circuit complexity, improved robustness to modulator coefficient variations, and reduced sensitivity to integrator nonlinearities Its performance is validated through behavioral simulations and compared to traditional /spl Delta//spl Sigma/ modulator structures 2) Signal transfer function (STF) This paper describes how the STF of a /spl Delta//spl Sigma/ modulator can be designed, independently of the NTF, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to help lower the power dissipation 3) Dynamic element matching (DEM) is also presented Data weighted averaging (DWA) has prevailed as the most practical DEM technique to linearize the internal digital-to-analog converter (DAC) of a multibit /spl Delta//spl Sigma/ modulator, especially when the number of DAC elements is large However, the occurrence of in-band signal-dependent tones, when using DWA at a low OSR, degrades the spurious-free dynamic range This paper proposes a simple technique, called pseudo DWA, to solve the DWA tone problem without sacrificing the signal-to-noise ratio Its implementation adds no extra delay in the /spl Delta//spl Sigma/ feedback loop and requires only minimal additional digital hardware Existing schemes for DWA tone reduction are also compared

High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling /spl Delta//spl Sigma/ ADCs for broad-band applications

Oversampling digital-to-analog (D/A) converters employing sigma-delta modulation noise shaping and single-bit quantization are attractive for use in digital audio applications because of their relaxed reconstruction filtering requirements and their tolerance of component mismatch. However, the use of a two-level D/A interface results in a large amount of out-of-band quantization noise that typically must be attenuated by a carefully designed analog reconstruction filter. This paper introduces a means of simplifying the reconstruction filter design through the use of a semidigital finite-impulse-response (FIR) filter. In particular, it describes an oversampling D/A converter wherein a current-mode semidigital reconstruction filter is used to implement a multilevel D/A interface that attenuates the out-of-band quantization noise without requiring precise component matching. An experimental implementation of the converter achieves a dynamic range of 94 dB and 72 dB attenuation of out-of-band quantization noise for a baseband of 20 kHz. The prototype converter, which consists of a linear interpolator, a second-order noise shaper, and a 128-tap semidigital FIR filter, dissipates 59 mW from a 5-V supply and occupies an active area of 3 mm/sup 2/ when integrated in a 1.2- mu m digital CMOS technology. >

A CMOS oversampling D/A converter with a current-mode semi-digital reconstruction filter

A two-channel differential 18-b bit-stream digital-to-analog converter implemented in a 2.5- mu m BiCMOS process with 7.3-mm/sup 2/ chip area is described. The circuit contains two identical 1-b D-to-A conversion channels on one single chip. Each channel consists of a digital input part, a switched-capacitor D-to-A network, and two high-performance operational amplifiers. Total harmonic distortion plus noise is better than -102 dB. The dynamic range is more than 108 dB, giving a true 18-b resolution. Output operational-amplifier distortion is below 120 dB at full-scale signal. System design considerations, implementation, and measured results of the IC are discussed. >

A bit-stream digital-to-analog converter with 18-b resolution

A monolithic dual high-speed 16-bit D/A converter is described. In the binary weighted current network a dynamic current divider is used to obtain the required high accuracy of the six most significant bits without any adjustment procedure or trimming technique. To construct the ten least significant bits a new approach is used to construct the passive divider stage based on emitter sealing of transistors. As the bit switches are optimized for fast-settling and low-glitch current, both converters can be used without extra sample-and-hold or deglitcher circuitry at sampling frequencies up to 200 kHz. The converter has a differential linearity of 0.5 LSB over a temperature range of -20 to +70/spl deg/ C. The high linearity of the converter results in a distortion of 0.001 percent over the audio band. The chip is processed in a standard bipolar process and the die size is 3.8 X 5.5 mm/sup 2/.

A Monolithic Dual 16-Bit D/A Converter

This codec chip is a complete two-channel low-voltage A/D and D/A conversion system with all associated filter functions. It is intended for portable digital audio recording equipment, such as DCC and MD as well as for digital personal communication systems. Each channel has its own independent A/D and D/A converters. The high degree of analog and digital integration results in an easily-applicable circuit with few external components and power consumption of only 40 mW for the D/A and 60 mW for the A/D, at a supply voltage of 2.7 V. The conversion techniques used yield a full-scale THD+N of -90 dB for both converters, and a dynamic range of 96 dBA for the A/D and 105 dBA for the D/A, representing a resolution of 16 and 18b respectively. The sample rate can be anywhere in the range from 28 to 54 kHz. The chip is fabricated in a low-threshold 0.8 /spl mu/m CMOS process.

A two-channel 16/18 b audio AD/DA including filter function with 60/40 mW power consumption at 2.7 V

A Bitstrearn Digital-to-analog Converter With 18b Resolution

A monolithic dual high-speed 16 bit D/A converter is described. Each converter can be used without extra sample-and-hold or deglitcher circuitry at sampling speeds up to 200 kHz. The converter has a differential linearity of typically 0.5 LSB over a temperature range of -20 to +70°C.

B.M.J. Kup

Papers

A bit-stream digital-to-analog converter with 18-b resolution

A Monolithic Dual 16-Bit D/A Converter

A two-channel 16/18 b audio AD/DA including filter function with 60/40 mW power consumption at 2.7 V

A Bitstrearn Digital-to-analog Converter With 18b Resolution

A Monolithic Dual 16 Bit D/A Converter