With their working mechanisms based on ion migration, the switching dynamics and electrical behaviour of memristive devices resemble those of synapses and neurons, making these devices promising candidates for brain-inspired computing. Built into large-scale crossbar arrays to form neural networks, they perform efficient in-memory computing with massive parallelism by directly using physical laws. The dynamical interactions between artificial synapses and neurons equip the networks with both supervised and unsupervised learning capabilities. Moreover, their ability to interface with analogue signals from sensors without analogue/digital conversions reduces the processing time and energy overhead. Although numerous simulations have indicated the potential of these networks for brain-inspired computing, experimental implementation of large-scale memristive arrays is still in its infancy. This Review looks at the progress, challenges and possible solutions for efficient brain-inspired computation with memristive implementations, both as accelerators for deep learning and as building blocks for spiking neural networks.

Memristive crossbar arrays for brain-inspired computing

Guided by brain-like ‘spiking’ computational frameworks, neuromorphic computing—brain-inspired computing for machine intelligence—promises to realize artificial intelligence while reducing the energy requirements of computing platforms. This interdisciplinary field began with the implementation of silicon circuits for biological neural routines, but has evolved to encompass the hardware implementation of algorithms with spike-based encoding and event-driven representations. Here we provide an overview of the developments in neuromorphic computing for both algorithms and hardware and highlight the fundamentals of learning and hardware frameworks. We discuss the main challenges and the future prospects of neuromorphic computing, with emphasis on algorithm–hardware codesign. The authors review the advantages and future prospects of neuromorphic computing, a multidisciplinary engineering concept for energy-efficient artificial intelligence with brain-inspired functionality.

Towards spike-based machine intelligence with neuromorphic computing.

Memristor crossbars offer reconfigurable non-volatile resistance states and could remove the speed and energy efficiency bottleneck in vector-matrix multiplication, a core computing task in signal and image processing. Using such systems to multiply an analogue-voltage-amplitude-vector by an analogue-conductance-matrix at a reasonably large scale has, however, proved challenging due to difficulties in device engineering and array integration. Here we show that reconfigurable memristor crossbars composed of hafnium oxide memristors on top of metal-oxide-semiconductor transistors are capable of analogue vector-matrix multiplication with array sizes of up to 128 × 64 cells. Our output precision (5–8 bits, depending on the array size) is the result of high device yield (99.8%) and the multilevel, stable states of the memristors, while the linear device current–voltage characteristics and low wire resistance between cells leads to high accuracy. With the large memristor crossbars, we demonstrate signal processing, image compression and convolutional filtering, which are expected to be important applications in the development of the Internet of Things (IoT) and edge computing.

Analogue signal and image processing with large memristor crossbars

This comprehensive review summarizes state of the art, challenges, and prospects of the neuro-inspired computing with emerging nonvolatile memory devices. First, we discuss the demand for developing neuro-inspired architecture beyond today’s von-Neumann architecture. Second, we summarize the various approaches to designing the neuromorphic hardware (digital versus analog, spiking versus nonspiking, online training versus offline training) and discuss why emerging nonvolatile memory is attractive for implementing the synapses in the neural network. Then, we discuss the desired device characteristics of the synaptic devices (e.g., multilevel states, weight update nonlinearity/asymmetry, variation/noise), and survey a few representative material systems and device prototypes reported in the literature that show the analog conductance tuning. These candidates include phase change memory, resistive memory, ferroelectric memory, floating-gate transistors, etc. Next, we introduce the crossbar array architecture to accelerate the weighted sum and weight update operations that are commonly used in the neuro-inspired machine learning algorithms, and review the recent progresses of array-level experimental demonstrations for pattern recognition tasks. In addition, we discuss the peripheral neuron circuit design issues and present a device-circuit-algorithm codesign methodology to evaluate the impact of nonideal device effects on the system-level performance (e.g., learning accuracy). Finally, we give an outlook on the customization of the learning algorithms for efficient hardware implementation.

Neuro-Inspired Computing With Emerging Nonvolatile Memorys

Journal of Applied physics,Vol.33 : 1962年に発表されたレオロジー関連の論文

Resistive switching memories have been identified as an enabling technology for a variety of emerging computing applications, including neuromorphic and logic-in-memory computing. For example, analog tuning of the memory state combined with high integration density of memristors is needed for very compact implementation of synapses, the most numerous devices in artificial neural networks and would be essential for low energy implementations of large-scale neuromorphic circuits. One way to increase effective memristor density is by vertical monolithical integration of memristor crossbar circuits. Previous work on such circuits have focused on their use for digital memory applications. Only limited device statistics was typically reported, not sufficient for understanding prospects for computing applications. Here we report fabrication and detailed characterization results for a bilayer stacked metal-oxide memristor crossbar circuits. The experimental results show excellent uniformity for the memristors in both crossbar layers. Moreover, the utilized low temperature process flow is CMOS compatible and can be extended to multi-layer stacking.

Highly-uniform multi-layer ReRAM crossbar circuits

We experimentally demonstrate classification of 4x4 binary images into 4 classes, using a 3-layer mixed-signal neuromorphic network ("MLP perceptron"), based on two passive 20x20 memristive crossbar arrays, board-integrated with discrete CMOS components. The network features 10 hidden-layer and 4 output-layer analog CMOS neurons and 428 metal-oxide memristors, i.e. is almost an order of magnitude more complex than any previously reported functional memristor circuit. Moreover, the inference operation of this classifier is performed entirely in the integrated hardware. To deal with larger crossbar arrays, we have developed a semi-automatic approach to their forming and testing, and compared several memristor training schemes for coping with imperfect behavior of these devices, as well as with variability of analog CMOS neurons. The effectiveness of the proposed schemes for defect and variation tolerance was verified experimentally using the implemented network and, additionally, by modeling the operation of a larger network, with 300 hidden-layer neurons, on the MNIST benchmark. Finally, we propose a simple modification of the implemented memristor-based vector-by-matrix multiplier to allow its operation in a wider temperature range.

Advancing Memristive Analog Neuromorphic Networks: Increasing Complexity, and Coping with Imperfect Hardware Components.

l integration with CMOS structures. The major drawbacks of nc-Si TFTs include low carrier mobility, threshold voltage (VT) shift under bias stress and lack ofp-channel operation due to unintentional n-type doping by oxygen impurity present in the nc-Si layer (2). We have fabricated nc-Si TFTs that minimize all the above drawbacks, and are thus well suited for use in neuromorphic applications. Top-gated TFTs with Cr source/drain and Al gate were fabricated with a staggered structure as shown in Fig. 1. The use ofCr as source/drain metal is to ensure low contact resistance (3). All TFTs used 200 nm Si02 as the gate dielectric. Devices with sub-micron dimensions were fabricated by patterning the source/drain metal and nc-Si channel with electron-beam lithography. The nc-Si channel material (80 nm thick) was deposited using PECVD, at 13.56 MHz, 125 W RF power, 0.9 Torr chamber pressure, and 2500 C deposition temperature in a 1:100 mixture of Siand H2• A turbo pump was fitted to the PECVD to reduce the background vacuum pressure to 6xlO- 6 Torr. XRD measurements were performed and the average crystal size in the nc-Si layer was calculated using Scherrer's formula (4) to be approximately 7 nm (Fig. 2). For device reliability comparison, we also fabricated another set of samples with similar processing except that the turbo-pump was not used with the PECVD in this case. Such samples had a much higher oxygen impurity concentration in the nc-Si layer. SIMS results from both types of samples confirm the reduction in oxygen concentration when the turbo-pump was used (Fig. 3). The electrical characteristics of the fabricated TFTs were measured and are shown in Fig. 4. The devices operate in both n-and p-channel regimes. In the n-channel regime, the devices have a threshold voltage of 3 V and subthreshold swing of 0.6 V/decade, whereas the corresponding values in the p-channel regime are-5 V and 0.65 V/decade. The field-effect mobility values in both regimes are plotted in Fig. 5. The maximum mobility for electrons is 20 cm2/V·s and that for holes is 3 cm2/V·s. The high hole mobility is ascribed to the low oxygen content in the nc-Si layer. Table 1 displays various device parameters at device lengths of 10 �m and 200 nm . The threshold voltage, subthreshold swing, and the peak electron mobility are not degraded at nanoscale dimensions (5). Two of the fabricated ambipolar transistors were connected to form an inverter circuit. Fig. 6 shows the output of such an inverter at different operating voltages. The WIL ratio of the pull-up transistor is five times that of the pull-down device to compensate for the lower hole mobility of the TFTs. The voltage gain when operating at 6 V is 12, which is the highest value that has been shown using ambipolar nc-Si TFTs (6). We attribute the high gain to the low subthreshold swing and low leakage current in the TFTs. We also investigated how the on-current of the TFTs scale with the device dimensions. The results (Fig. 7) indicate that the on-current (measured at VG=5 V, VD=5 V) scales fairly linearly with device width for both n­ channel and p-channel operation down to a channel width of 200 nm . The on-current also scales linearly with channel length down to 200 nm . Thus scaling the device dimensions is not detrimental to the device performance, allowing such devices to be used in architectures that require high density. Finally, the shift in threshold voltage of the TFTs was measured after the application of different voltage stresses. The results (shown in Fig. 8) indicate that the degradation is significantly reduced for the samples with low oxygen concentration. Of the two accepted V T degradation mechanisms in nc-Si TFTs (7), charge trapping in the gate dielectric is reversible. The observed V T shift did not recover after a rest period of several hours or under the application of negative gate bias, suggesting that the shift is irreversible. Thus, under the applied bias conditions, defect creation in the channel layer is the principal V T degradation mechanism. The results also suggest that the oxygen impurity present in the nc-Si layer plays an important role in the defect creation.

http://ieeexplore.ieee.org/iel5/5981430/5994397/05994433.pdf

TFTs with Submicron Dimensions and Reduced Threshold Voltage Shift

A wide variety of two-dimensional (2D) metal dichalcogenide compounds have recently attracted much research interest due to their very high photoresponsivities (R) making them excellent candidates for optoelectronic applications. High R in 2D photoconductors is associated with trap state dynamics leading to a photogating effect, which is often manifested by a fractional power dependence (γ) of the photocurrent (Iph) at an effective illumination intensity (Peff). Here we present photoconductivity studies as a function of gate voltages, over a wide temperature range (20 K to 300 K) of field-effect transistors fabricated using thin layers of mechanically exfoliated Rhenium Diselenide (ReSe2). We obtain very high responsivities R ∼ 16500 A/W and external quantum efficiency (EQE) ∼ 3.2 × 106% (at 140 K, Vg = 60 V and Peff = 0.2 nW). A strong correlation between R and γ was established by investigating the dependence of these two quantities at various gate voltages and over a wide range of temperatures. Such correlations indicate the importance of trap state mediated photogating and its role in promoting high photo-responsivities in these materials. We believe such correlations can offer valuable insights for the design and development of high-performance photoactive devices using 2D materials.

Photogating-driven enhanced responsivity in a few-layered ReSe2 phototransistor

Hydrogenated nano-crystalline-silicon (nc-Si) thin-film transistors (TFTs) are primary candidates for use in neuromorphic circuits and systems [1]. Such devices can be fabricated at low temperatures and over large areas, allowing cheap processing and three-dimensional integration with CMOS structures. The major drawbacks of nc-Si TFTs include low carrier mobility, threshold voltage (V T ) shift under bias stress and lack of p-channel operation due to unintentional n-type doping by oxygen impurity present in the nc-Si layer [2]. We have fabricated nc-Si TFTs that minimize all the above drawbacks, and are thus well suited for use in neuromorphic applications.

Bhaswar Chakrabarti

Papers

Highly-uniform multi-layer ReRAM crossbar circuits

Advancing Memristive Analog Neuromorphic Networks: Increasing Complexity, and Coping with Imperfect Hardware Components.

TFTs with Submicron Dimensions and Reduced Threshold Voltage Shift

Photogating-driven enhanced responsivity in a few-layered ReSe2 phototransistor

Ambipolar nano-crystalline-silicon TFTs with submicron dimensions and reduced threshold voltage shift