Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

Various methods and systems for determining a position of inspection data in design data space are provided. One computer-implemented method includes determining a centroid of an alignment target formed on a wafer using an image of the alignment target acquired by imaging the wafer. The method also includes aligning the centroid to a centroid of a geometrical shape describing the alignment target. In addition, the method includes assigning a design data space position of the centroid of the alignment target as a position of the centroid of the geometrical shape in the design data space. The method further includes determining a position of inspection data acquired for the wafer in the design data space based on the design data space position of the centroid of the alignment target.

Methods and systems for determining a position of inspection data in design data space

Computer-implemented methods and systems for detecting defects in a reticle design pattern are provided. One computer-implemented method includes acquiring images of the reticle design pattern using a sensor disposed on a substrate arranged proximate to an image plane of an exposure system configured to perform a wafer printing process using the reticle design pattern. The images illustrate how the reticle design pattern will be projected on a wafer by the exposure system at different values of one or more parameters of the wafer printing process. The method also includes detecting defects in the reticle design pattern based on a comparison of two or more of the images corresponding to two or more of the different values.

Methods and systems for detecting defects in a reticle design pattern

One embodiment of a method for process window optimized optical proximity correction includes applying optical proximity corrections to a design layout, simulating a lithography process using the post-OPC layout and models of the lithography process at a plurality of process conditions to produce a plurality of simulated resist images. A weighted average error in the critical dimension or other contour metric for each edge segment of each feature in the design layout is determined, wherein the weighted average error is an offset between the contour metric at each process condition and the contour metric at nominal condition averaged over the plurality of process conditions. A retarget value for the contour metric for each edge segment is determined using the weighted average error and applied to the design layout prior to applying further optical proximity corrections.

Method for process window optimized optical proximity correction

Systems and methods for creating inspection recipes are provided. One computer-implemented method for creating an inspection recipe includes acquiring a first design and one or more characteristics of output of an inspection system for a wafer on which the first design is printed using a manufacturing process. The method also includes creating an inspection recipe for a second design using the first design and the one or more characteristics of the output acquired for the wafer on which the first design is printed. The first and second designs are different. The inspection recipe will be used for inspecting wafers after the second design is printed on the wafers using the manufacturing process.

Systems and methods for creating inspection recipes

Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs are provided. One method includes generating simulated images illustrating how each of the different reticle designs will be printed on a wafer at different values of one or more parameters of the wafer printing process. The method also includes detecting defects in each of the different reticle designs using the simulated images. In addition, the method includes determining a process window for the wafer printing process for each of the different reticle designs based on results of the detecting step.

Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs

Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer are provided. One method includes generating simulated images of the reticle features printed on the wafer using different generated models for a set of different values of exposure conditions. The method also includes determining one or more characteristics of the reticle features of the simulated images. In addition, the method includes comparing the one or more characteristics of the reticle features of the simulated images to one or more characteristics of the reticle features printed on the wafer using a lithography process. The method further includes selecting one of the different generated models as the model to be used for predicting the printability of the reticle features based on results of the comparing step.

Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer

As the industry moves towards sub-65nm technology nodes, the mask inspection, with increased sensitivity
and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect
counts pose great challenges in the post inspection defect classification and disposition: which defect is real
defect, and among the real defects, which defect should be repaired and how to verify the post-repair
defects.
In this paper, we address the challenges in mask defect verification and disposition, in particular, in post
repair defect verification by an efficient methodology, using SEM mask defect images, and optical
inspection mask defects images (only for verification of phase and transmission related defects).
We will demonstrate the flow using programmed mask defects in sub-65nm technology node design. In
total 20 types of defects were designed including defects found in typical real circuit environments with 30
different sizes designed for each type. The SEM image was taken for each programmed defect after the test
mask was made. Selected defects were repaired and SEM images from the test mask were taken again.
Wafers were printed with the test mask before and after repair as defect printability references.
A software tool SMDD-Simulation based Mask Defect Disposition-has been used in this study. The
software is used to extract edges from the mask SEM images and convert them into polygons to save in
GDSII format. Then, the converted polygons from the SEM images were filled with the correct tone to
form mask patterns and were merged back into the original GDSII design file. This merge is for the
purpose of contour simulation-since normally the SEM images cover only small area (~1 μm) and
accurate simulation requires including larger area of optical proximity effect. With lithography process
model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If
such complicated model is not available, a simple optical model can be used to get simulated aerial image
intensity in the AOI. With built-in contour analysis functions, the SMDD software can easily compare the
contour (or intensity) differences between defect pattern and normal pattern. With user provided judging
criteria, this software can be easily disposition the defect based on contour comparison. In addition, process
sensitivity properties, like MEEF and NILS, can be readily obtained in the AOI with a lithography model,
which will make mask defect disposition criteria more intelligent.

/pdf/simulation-based-mask-defect-repair-verification-and-4ezc3cv7bk.pdf

Simulation based mask defect repair verification and disposition

Despite great effort before design tapeout, there are still some pattern related systematic defects showing up in production,
which impact product yield. Through various check points in the production life cycle endeavor is made to detect these
defective patterns. It is seen that apart from the known defective patterns, slight variations of polygon sizes and shapes in the
known defective patterns also cause yield loss. This complexity is further compounded when interactions among multiple
process layers causes the defect. Normally the exact pattern matching techniques cannot detect these variations of the
defective patterns. With the currently existing tools in the fab it is a challenge to define the 'sensitive patterns', which are
arbitrary variations in the known 'defective patterns'. A design based approach has been successfully experimented on
product wafers to detect yield impacting defects that greatly reduces the TAT for hotspot analysis and also provides
optimized care area definition to enable high sensitivity wafer inspection.
A novel Rule based pattern search technique developed by Anchor Semiconductor has been used to find sensitive patterns in
the full chip design. This technique allows GUI based pattern search rule generation like, edge move or edge-to-edge
distance range, so that any variations of a particular sensitive pattern can be captured and flagged. Especially the pattern rules
involving multiple process layers, like M1-V1-M2, can be defined easily using this technique. Apart from using this novel
pattern search technique, design signatures are also extracted around the defect locations in the wafer and used in defect
classification. This enhanced defect classification greatly helps in determining most critical defects among the total defect
population. The effectiveness of this technique has been established through design to defect correlation and SEM
verification.
In this paper we will report details of the design based experiments that were successfully run on multiple process layers in
production device.

Yield impacting systematic defects search and management

Optical proximity corrections (OPC) applied to design layouts are targeted for the nominal process condition F o E o that maintains manufacturing throughput and yiel d. For designs at 130 nm and above, this is usually sufficient to provide the needed resolution enhancement te chnology (RET) corrections for high-yield manufacturing. However, for sub-100 nm designs, lack of feature fidelity across the process window becomes a significant contributor to yield loss. It becomes critical to simulate across the lithography process window to predict feature behavior over a wide range of focus and exposure (FE) conditions. KLA-Tencors DesignScan tool simulates the performance of a design across the process window and detects any defects which are then flagged for repair. In the conventional OPC flow, correction of defects en tails changing the OPC recipe and redecorating the entire layout. Aprios reconfigurable OPC technology allows one to compute more aggressive OPC corrections at the error locations. This reconfigured OPC replaces the original corrections only at the error locations. This allows prior OPC results to be re-used. The halo or boundary areas associated with the stitching of the modified OPC are simulated and verified and the results are converge d back into the layout. This allows the designer to start with a nominal OPC design and by applying reconfigurable OPC technology, eliminate printability errors in the process window, expand the process window, resulting in more robust design performance across the process win dow. This mask design in spection and optimization method improves yield and shortens cycle time to first wafers, thus providing closure for the design to manufacturing loop. Keywords: OPC, halo, optical proximity correction, RET, OPC reconfiguration, process window, Halo-OPC, DesignScan

Bo Su

Papers

Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs

Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer

Simulation based mask defect repair verification and disposition

Yield impacting systematic defects search and management

Applying reconfigurable RET across process window to create more robust manufacturing designs