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Proceedings ArticleDOI

Simulation based mask defect repair verification and disposition

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TLDR
In this paper, a software tool called SMDD-Simulation based Mask Defect Disposition (SMDD) is used to extract edges from the mask SEM images and convert them into polygons to save in the GDSII format.
Abstract
As the industry moves towards sub-65nm technology nodes, the mask inspection, with increased sensitivity and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect counts pose great challenges in the post inspection defect classification and disposition: which defect is real defect, and among the real defects, which defect should be repaired and how to verify the post-repair defects. In this paper, we address the challenges in mask defect verification and disposition, in particular, in post repair defect verification by an efficient methodology, using SEM mask defect images, and optical inspection mask defects images (only for verification of phase and transmission related defects). We will demonstrate the flow using programmed mask defects in sub-65nm technology node design. In total 20 types of defects were designed including defects found in typical real circuit environments with 30 different sizes designed for each type. The SEM image was taken for each programmed defect after the test mask was made. Selected defects were repaired and SEM images from the test mask were taken again. Wafers were printed with the test mask before and after repair as defect printability references. A software tool SMDD-Simulation based Mask Defect Disposition-has been used in this study. The software is used to extract edges from the mask SEM images and convert them into polygons to save in GDSII format. Then, the converted polygons from the SEM images were filled with the correct tone to form mask patterns and were merged back into the original GDSII design file. This merge is for the purpose of contour simulation-since normally the SEM images cover only small area (~1 μm) and accurate simulation requires including larger area of optical proximity effect. With lithography process model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If such complicated model is not available, a simple optical model can be used to get simulated aerial image intensity in the AOI. With built-in contour analysis functions, the SMDD software can easily compare the contour (or intensity) differences between defect pattern and normal pattern. With user provided judging criteria, this software can be easily disposition the defect based on contour comparison. In addition, process sensitivity properties, like MEEF and NILS, can be readily obtained in the AOI with a lithography model, which will make mask defect disposition criteria more intelligent.

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Lithographic plane check for mask processing

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References
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Proceedings ArticleDOI

High resolution inspection with wafer plane die: database defect detection

TL;DR: Wafer Plane Inspection (WPI) detector as mentioned in this paper is a state-of-the-art detector for high-resolution reticle inspection that is based on a modeled image of how the mask would actually print in the photoresist.
Proceedings ArticleDOI

Post-OPC verification using a full-chip pattern-based simulation verification method

TL;DR: In this paper, a full-chip pattern-based simulation verification flow serves both OPC model and recipe development as well as post-OPC verification after production release of the OPC.
Proceedings ArticleDOI

Auto-classification and simulation of mask defects using SEM and CAD images

TL;DR: In this paper, a combination of a SEM defect review tool and defect disposition and simulation software is proposed, which uses high-resolution SEM images of defects to do defect review, defect disposition, and wafer printing simulation of defects automatically or manually.
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