The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.

Lithographic plane check for mask processing

Despite great effort before design tapeout, there are still some pattern related systematic defects showing up in production,
which impact product yield. Through various check points in the production life cycle endeavor is made to detect these
defective patterns. It is seen that apart from the known defective patterns, slight variations of polygon sizes and shapes in the
known defective patterns also cause yield loss. This complexity is further compounded when interactions among multiple
process layers causes the defect. Normally the exact pattern matching techniques cannot detect these variations of the
defective patterns. With the currently existing tools in the fab it is a challenge to define the 'sensitive patterns', which are
arbitrary variations in the known 'defective patterns'. A design based approach has been successfully experimented on
product wafers to detect yield impacting defects that greatly reduces the TAT for hotspot analysis and also provides
optimized care area definition to enable high sensitivity wafer inspection.
A novel Rule based pattern search technique developed by Anchor Semiconductor has been used to find sensitive patterns in
the full chip design. This technique allows GUI based pattern search rule generation like, edge move or edge-to-edge
distance range, so that any variations of a particular sensitive pattern can be captured and flagged. Especially the pattern rules
involving multiple process layers, like M1-V1-M2, can be defined easily using this technique. Apart from using this novel
pattern search technique, design signatures are also extracted around the defect locations in the wafer and used in defect
classification. This enhanced defect classification greatly helps in determining most critical defects among the total defect
population. The effectiveness of this technique has been established through design to defect correlation and SEM
verification.
In this paper we will report details of the design based experiments that were successfully run on multiple process layers in
production device.

Yield impacting systematic defects search and management

As device features continue to shrink, achieving acceptable yields becomes increasingly challenging. In the photolithography process, mask error is one of the most critical error sources, since any imperfections on a mask will be amplified and transferred onto a wafer due to Mask Error Enhancement Factor (MEEF) [1]. Furthermore, due to complexity of lithography optical proximity effect correction in advanced technology nodes, more and more 2D structures are applied into mask patterns. Furthermore, more 2D pattern configurations are susceptible to pattering failures due to their much high MEEF factor than 1D pattern. As a result, the conventional mask error control mechanisms for 1D [2] [3] [4] only, such as mean-to-target (MTT) and CD uniformity, are no longer adequate to deal with high MEEF 2D structures. In this paper, a novel 2D structure mask error monitoring technique is introduced to prevent fatal wafer printing errors such as CD error, line-end pull back and other pattern distortions to ensure high quality mask manufacturing and to improve wafer yield in advanced technology nodes. We will demonstrate the flow using typical 2D structure test patterns in 28nm technology node design or beyond. The SEM image would be taken and measured by this novel technique are used to monitor mask fidelity performance. This monitoring technique is based on Image-to-layout, as one of Anchor Semiconductor’s pattern centric techniques, which can extract contour and convert it into pattern layouts from SEM or optical image of masks. Further pattern signature analysis can be performed on the pattern (inner /outer vertex, space distance and edge distance), so that we can quickly identify target locations for 2D pattern measurements. We monitor the severity of 2D corner rounding on selected 28nm design rule masks by Pattern Fidelity (PF) ratio and correlate them with wafer printing results. 2D pattern measurement techniques and PF ratio monitoring system from SEM image is an effective approach to ensure high quality mask making in 28nm and advanced technology nodes. This PF ratio monitoring from 2D pattern SEM images is an effective approach to ensure high quality mask making in advanced 28nm node and beyond, which can overcome the inadequacy of current 1D measurement only method, especially for the masks are generated without source mask optimization (SMO) [6].

Enhanced photomask quality control by 2D structures monitoring using auto image-to-layout method on advanced 28nm technology node or beyond

Rigorous patterning control at critical wafer process steps of semiconductor fabrication is done to ensure integrity of the manufacturing process. At times, still with the entire existing process control infrastructure, we run into defect issues. Here we report an innovative methodology of Pattern Monitor that complements the existing approach and consistently detects critical defects on wafer that are hard to find using conventional wafer inspection tools. The unique integrated pattern centric approach puts this method apart from all the current inline tools. The Die-to-Database Pattern Monitor (D2DB-PM) solution has been applied to understand the evolution of pattern deformation through process integration engineering. A pattern centric engine is the key to this successful solution that is used to process large volumes of already existing Scanning Electron Microscope (SEM) images to perform Die-to-Database shape and critical dimension evaluation to detect deviations in the patterning behavior. This solution helped to resolve the limited Critical dimension (CD) measurement constraint that is otherwise associated with Critical Dimension Scanning Electron Microscope (CDSEM) measurement. In this paper we report the results from this innovative solution to detect process marginality and also verify the improved patterning behavior after the process fix is implemented.

Critical defect detection, monitoring and fix through process integration engineering by using D2DB pattern monitor solution

The 3D NAND (three-dimensional NAND type) has rapidly become the standard technology for enterprise flash memories, and is also gaining widespread use in other applications. Continued manufacturing process improvements are essential in delivering memory devices with higher I/O performance, higher bit density, and lower cost. Current 3D NAND technology involves process steps that form array and peripheral CMOS (Complementary Metal-Oxide-Semiconductor) regions side-by-side, resulting in waste of silicon real estate and film stress compromises, and limits the paths of making advanced 3D NAND devices. An innovative architecture was invented to overcome these challenges by connecting two wafers electrically through millions of metal VIAs (Vertical Interconnect Access) simultaneously across the whole wafer in one process step [1]. A highly accurate and efficient metrology is required to monitor the VIA interface due to the increased process complexity and precision requirements. With the advanced processing of AFM (Atomic Force Microscopy) images, highly accurate and precise measurements have been achieved. An inline pattern-centric metrology solution that is designed for high volume mass production of high-performance 3D NAND is presented in this paper.

Novel pattern-centric solution for high performance 3D NAND VIA dishing metrology

As the industry moves towards sub-65nm technology nodes, the mask inspection, with increased sensitivity
and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect
counts pose great challenges in the post inspection defect classification and disposition: which defect is real
defect, and among the real defects, which defect should be repaired and how to verify the post-repair
defects.
In this paper, we address the challenges in mask defect verification and disposition, in particular, in post
repair defect verification by an efficient methodology, using SEM mask defect images, and optical
inspection mask defects images (only for verification of phase and transmission related defects).
We will demonstrate the flow using programmed mask defects in sub-65nm technology node design. In
total 20 types of defects were designed including defects found in typical real circuit environments with 30
different sizes designed for each type. The SEM image was taken for each programmed defect after the test
mask was made. Selected defects were repaired and SEM images from the test mask were taken again.
Wafers were printed with the test mask before and after repair as defect printability references.
A software tool SMDD-Simulation based Mask Defect Disposition-has been used in this study. The
software is used to extract edges from the mask SEM images and convert them into polygons to save in
GDSII format. Then, the converted polygons from the SEM images were filled with the correct tone to
form mask patterns and were merged back into the original GDSII design file. This merge is for the
purpose of contour simulation-since normally the SEM images cover only small area (~1 μm) and
accurate simulation requires including larger area of optical proximity effect. With lithography process
model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If
such complicated model is not available, a simple optical model can be used to get simulated aerial image
intensity in the AOI. With built-in contour analysis functions, the SMDD software can easily compare the
contour (or intensity) differences between defect pattern and normal pattern. With user provided judging
criteria, this software can be easily disposition the defect based on contour comparison. In addition, process
sensitivity properties, like MEEF and NILS, can be readily obtained in the AOI with a lithography model,
which will make mask defect disposition criteria more intelligent.

/pdf/simulation-based-mask-defect-repair-verification-and-4ezc3cv7bk.pdf

Simulation based mask defect repair verification and disposition

In photomask production environments, increasing productivity of defect inspection and improving fidelity of defect
classification are important for mask makers to improve capacity of defect inspection tools and to enhance quality of
production. In particular, defect classification time corresponds directly to the cost and the cycle time of mask
manufacturing and new product development. KLA-Tencor has introduced an automatic defect grouping tool
"ReviewSmart" which automatically bins defects with high fidelity. ReviewSmart has been reported in engineering R&D
and evaluation. In this paper, we focus on implementation of ReviewSmart in photomask production. 592 plates
were processed during the evaluation period. Those plates are for products of logic, memory and flash. Technology
nodes are from 65nm to 180nm. With optimized production setting, the automatic defect grouping tool - ReviewSmart
improves productivity of defect inspection by 7% with 100% fidelity. In addition to improve productivity, ReviewSmart
is helpful to classify aggressive OPC caused nuisance, troubleshoot process issues and expedite product development and
improve usable inspection sensitivity as well.

Skin Zhang

Papers

Simulation based mask defect repair verification and disposition

Implementation of an efficient defect classification method in photomask mass production