We investigate the breakdown (V/sub br/) enhancement potential of the field plate (FP) technique in the context of AlGaN/GaN power HEMTs. A comprehensive account of the critical geometrical and material variables controlling the field distribution under the FP is provided. A systematic procedure is given for designing a FP device, using two-dimensional (2-D) simulation, to obtain the maximum V/sub br/, with minimum degradation in on-resistance and frequency response. It is found that significantly higher V/sub br/ can be achieved by raising the dielectric constant (/spl epsi//sub i/) of the insulator beneath the FP. Simulation gave the following estimates. The FP can improve the V/sub br/ by a factor of 2.8-5.1, depending on the 2-DEG concentration (n/sub s/) and /spl epsi//sub i/. For n/sub s/=1/spl times/10/sup 13//cm/sup 2/, the V/sub br/ can be raised from 123 V to 630 V, using a 2.2 /spl mu/m FP on a 0.8 /spl mu/m silicon nitride, and 4.7 /spl mu/m gate-drain separation. The methodology of this paper can be extended to the design of FP structures in other lateral FETs, such as MESFETs and LD-MOSFETs.

Enhancement of breakdown voltage in AlGaN/GaN high electron mobility transistors using a field plate

A method of fabricating a light emitting diode, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer, is provided. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure.

Deep ultraviolet light emitting diode

An experimental study of the mechanism of RF current collapse removal in high-power nitride-based HFETs is presented. The results show that the conductivity of the dielectric material under the field plate plays a crucial role in the current collapse removal. Identical geometry field plated HFETs differing only in the FP dielectric conductivity show varying degree of current collapse removal. Devices with semiconducting dielectric layers exhibit perfectly linear RF power - drain bias dependence with the output powers of 20 W/mm at 55 V drain bias with essentially no current collapse. A trapped charge discharging model is presented to explain the removal of current collapse in FPd devices.

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Mechanism of current collapse removal in field-plated nitride HFETs

The termination of the depletion zone towards the non-depleted part of silicon affects the total device leakage current, the long term stability, the noise level and the radiation hardness of silicon detectors. This paper describes computer simulations and experiments to develop guard ring structures for use in silicon detectors requiring thick depletion layers, high operating voltages and biasing beyond depletion without increase in the leakage current and the noise. Computer simulation of a simplified structure is used to understand the influence from the oxide charges and the substrate doping concentration for a segmented guard structure with several floating diffusion strips. Results from the simulations are compared with measurements on devices. The numerical results are found to be in agreement with experimental data. It is found that segmented guard structures with floating diffusion strips have high breakdown voltages and low leakage currents. The effects of floating metal field plates over the oxide between the floating diffusion strips are studied on two different guard structures by measuring the potential on the diffusion strips and the leakage currents in the guard and active diode. The results show that floating intermediate field plates reduces the influence from oxide charges and stabilises the device against environmental influence.

Guard ring design for high voltage operation of silicon detectors

A lateral double-diffusion MOSFET with a uniform high-permittivity (HK) dielectric field plate (FP) is manufactured and presented in this letter. The HK dielectric FP is capable of cutting both electric peak fields at the channel p-n junction and the edge of FP, providing higher breakdown voltage (BV) based on a novel mechanism. The Pb(Zr0.53, Ti0.47)O3 (PZT) is taken as the HK dielectric material for its large preanneal permittivity. The test results indicate that, based on two identical devices except for the dielectric material, the BV of the one with PZT FP is more than three times of that of the counterpart with a SiO2 dielectric, approximately 350 and 100 V, respectively.

Analysis and Fabrication of an LDMOS With High-Permittivity Dielectric

The breakdown voltages of planar junctions (both nonpunchthrough and punchthrough cases) equipped with field plates and guard rings are determined by evaluating the ionization integral using the potential distribution computed by solving Poisson's equation in two-dimensions by a finite difference method. The influence of various parameters, such as substrate doping concentration, n-layer thickness, field oxide thickness, cylindrical junction curvature, field plate width, and the spacing between field plate and guard ring, on the breakdown voltage is extensively studied. It is shown that an optimum value exists for the field oxide thickness to realize maximum breakdown voltage. The study also shows that the optimum oxide thickness depends upon cylindrical junction curvature, substrate doping concentration, and n-layer thickness. It is further shown that the permittivity of a passivant dielectric layer deposited over field plate structure influences the breakdown voltage when breakdown takes place at the field plate edge. The numerical results are compared with the experimental data, and good agreement between the two is observed. Based on this two-dimensional study, design guidelines are provided for achieving breakdown voltages close to maximum realizable values, by conserving the device area and reducing the ionization at the field plant edge. The results presented clearly demonstrate the superiority of the field plate design using punchthrough structures over nonpunchthrough structures in realizing a given breakdown voltage. >

Two-dimensional analysis and design considerations of high-voltage planar junctions equipped with field plate and guard ring

The influences of the field oxide thickness and the junction depth on the breakdown voltage of semi-insulator passivated planar junctions with the field plate are investigated using a 2D simulator. This is done by analyzing the two extreme situations: the planar junction with an infinitely long field plate, and the deep-depleted MOS structure having a finite size. This rather unconventional approach has offered a new physical insight into the role of the metal field plate and has revealed that the severe field crowding associated with a shallow planar junction can be greatly suppressed by using a thin field oxide. The breakdown voltage and the optimal field oxide thickness of the semi-insulator passivated field plate structures remain nearly constant over a wide variation in the junction depth, and therefore such structures are attractive for realizing high-voltages in vertical devices fabricated by low-voltage IC technology. The influences of the field plate width and the inter-electrode spacing are studied by the conventional approach, and a simple and widely applicable design guideline is given for both the nonpunchthrough and the punchthrough type structures. The influence of the surface charge in the range 0 to 10/sup 12/ cm/sup -2/ is found to be negligible. The semi-insulator passivated and the dielectric passivated field plate structures are compared under optimal conditions. This suggests that the semi-insulator passivated structures are attractive when thin field oxide and a shallow planar junction are needed and that the dielectric passivated structures are better when compactness is desired. >

Analysis and optimal design of semi-insulator passivated high-voltage field plate structures and comparison with dielectric passivated structures

Using the recently developed two-dimensional simulator STAAB, the breakdown voltage of the field plate and field-limiting ring junction termination techniques is numerically compared for various values of junction depth, lateral width, and oxide fixed charge. The computed results demonstrate the superiority of the field plate technique over the field-limiting ring technique for planar shallow-junction high-voltage devices, both discrete and integrated. >

C.B. Goud

Papers

Two-dimensional analysis and design considerations of high-voltage planar junctions equipped with field plate and guard ring

Analysis and optimal design of semi-insulator passivated high-voltage field plate structures and comparison with dielectric passivated structures

Breakdown voltage of field plate and field-limiting ring techniques: numerical comparison