Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

Basic mechanisms and modeling of single-event upset in digital microelectronics

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

Radiation effects in SOI technologies

Total ionizing dose radiation effects on the electrical properties of metal-oxide-semiconductor devices and integrated circuits are complex in nature and have changed much during decades of device evolution. These effects are caused by radiation-induced charge buildup in oxide and interfacial regions. This paper presents an overview of these radiation-induced effects, their dependencies, and the many different approaches to their mitigation.

Radiation effects and hardening of MOS technology: devices and circuits

The authors review various single event effects (SEE) testing and rate prediction methodologies and recommend standard approaches. This discussion is limited to single event upset (SEU) rate prediction for direct-ionization-induced effects. The standard approach being recommended is based partially on a different way of viewing the results of SEU cross-section measurements. The measurements are not measuring a distribution of cross-sections. They are measuring a distribution of device sensitivities, due to differences of sensitive region critical charges and to differences of charge collection. The linear energy transfer (LET), at which 50% of the cell population upsets, corresponds to the charge deposition necessary to upset the median cell in the circuit array. The threshold LET corresponds to the most sensitive region being hit in its most sensitive location, and does not represent the entire array. The shape of the cross-section curve is described by an integral Weibull distribution. The upset rate for a device should then be calculated using the differential rate of each sensitive region, combined with an integral weighting given by the Weibull distribution that describes the measured cross-section curve. >

Rate prediction for single event effects-a critique

Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFET's in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

This paper presents the first measurements of transient radiation effects on SOI discrete devices and an LSI memory. A commercially processed LSI SOI memory, a 4K × 1 SRAM on SIMOX, was tested for SEU, and transient ionizing radiation effects as a function of bias conditions and dose rate. The SEU error rate was found to be between 1.5 and 2.5 × 10-8 errors/bit-day for the 10% worst-case orbit model. The output voltage logic upset level was greater than 1.6 × 1010 rad(Si)/sec for Vcc supply voltage variations of -10% and +20% with Vsub at -10 V. For the discrete devices and memory, the measured transient photocurrents were larger than the calculated volumetric photocurrent generated in the active device region. This increased transient response is postulated to be due to the gain of the parasitic phototransistor of the dielectrically isolated MOS device.

Transient Radiation Effects in SOI Memories

The total dose characteristics of CMOS devices fabricated in oxygen implanted buried oxide silicon-on-insulator (SOI) substrates with different post-implant annealing processes are studied. The threshold voltage shift, subthreshold slope degradation and mobility degradation of front channel SOI/CMOS devices are measured to be the same as those of bulk devices processed identically. Negative substrate bias lowers the threshold voltage shift of back channel SOI transistors, while not affecting the front channel characteristics. Under present processing conditions, the radiation characteristics of front channel devices are independent of the postoxygen-implant annealing temperature. Oxygen precipitates at the silicon/buried oxide interface enhance interface state generation of the back channel devices during irradiation.

Total Dose Characterizations of CMOS Devices in Oxygen Implanted Silicon-on-Insulator

A static random access memory (SRAM) cell with cross-coupled stacked CMOS inverters is demonstrated for the first time. In this approach, CMOS inverters are fabricated with a laser recrystallized p-channel device stacked on top of and sharing the gate with a bulk n-channel device using a modified two-polysilicon n-MOS process. The memory cell has been exercised through the write and read cycles with external signal generators while the output is buffered by an on-chip, stacked-CMOS-inverter-based amplifier.

Stacked CMOS SRAM cell

p-channel MOSFETs in LPCVD polysilicon have been built. Grain boundary passivation using a plasma of hydrogen has been explored as a means of improving the device performance. Dramatic enhancement of drive current and curtailment of leakage current have been observed. The devices are well suited for application as load elements in CMOS static RAMs.

Effects of grain boundary passivation on the characteristics of p-channel MOSFETs in LPCVD polysilicon

p-channel MOSFET's have been fabricated in LPCVD polysilicon. A 5000-A n+poly acts as the gate electrode on which a 500-A thermal oxide is grown to act as the gate insulator. Then a 1500-A LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm2/V.s. The drain-to-source breakdown voltage exceeds -20 V.

C.-E. Chen

Papers

Transient Radiation Effects in SOI Memories

Total Dose Characterizations of CMOS Devices in Oxygen Implanted Silicon-on-Insulator

Stacked CMOS SRAM cell

Effects of grain boundary passivation on the characteristics of p-channel MOSFETs in LPCVD polysilicon

p-Channel MOSFET's in LPCVD PolySilicon