Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approach to overcome the variation problem. Existing non-tree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wire-length. In this paper, we suggest to construct a low cost non-tree clock network by inserting cross links in a given clock tree. The effects of the link insertion on clock skew variability are analyzed. Based on the analysis, we propose two link insertion schemes that can quickly convert a clock tree to a non-tree with significantly lower skew variability and very limited wirelength increase. In these schemes, the complicated non-tree delay computation is circumvented. Further, they can be applied to the recently popular non-zero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2 increase of wirelength.

Reducing clock skew variability via cross links

Deformations in interconnect due to process variations can lead to significant performance degradation in deep sub-micron circuits. Timing analyzers attempt to capture the effects of variation on delay with simplified models. The timing verification of RC or RLC networks requires the substitution of such simplified models with spatial stochastic processes that capture the random nature of process variations. The present work proposes a new and viable method to compute the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by using the Galerkin approach of minimizing the Hilbert space norm of the residual error. The key advance of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called OPERA, results from OPERA simulations on commercial design test cases match well with those from the classical Monte Carlo SPICE simulations and from perturbation methods. Additionally OPERA shows good computational efficiency: speedup factor of 60 has been observed over Monte Carlo SPICE simulations.

Stochastic analysis of interconnect performance in the presence of process variations

This tutorial reviews statistical circuit modeling and optimization and its applications in integrated circuit design. Motivated by a discussion of the importance of statistical design techniques, it introduces the primary concepts and discusses the main techniques used for statistical modeling, analysis and optimization. It also considers some of the important open questions.

Statistical circuit modeling and optimization

In this paper, a technology computer-aided design (TCAD) driven method for accurate prediction of the performance spread of integrated circuits due to process variations is presented. The methodology starts with the development of the nominal process recipe and process simulators are calibrated to an existing process to obtain nominal device characteristics. After determining nominal process parameters, their variations are introduced followed by screening experiments to determine the relative effects of given process variations on the input-output delay and the average power dissipation in a circuit. Response surface models (RSMs) are then generated based on critical process factors identified. Process parameter optimization is performed using these RSM models to tune the mean circuit performance and to improve the yield. This methodology is demonstrated on a 33-stage ring oscillator manufactured with a CMOS design flow. The proposed methodology maps the process domain to design space, and plays a key role in design for manufacturability (DFM) to quantify direct impact of the process variations on circuits.

Statistical methods for the estimation of process variation effects on circuit operation

Accurate clock skew budgets are important for microprocessor designers to avoid hold-time failures and to properly allocate resources when optimizing global and local paths. Many published clock skew budgets neglect voltage jitter and process variation, which are becoming dominant factors in otherwise balanced H-trees. However, worst-case process variation assumptions are severely pessimistic. This paper describes the major sources of clock skew in a microprocessor using a modified H-tree and applies the model to a second-generation Itanium-M processor family microprocessor currently under design. Monte Carlo simulation is used to develop statistical clock skew budgets for setup and hold time constraints in a four-level skew hierarchy. Voltage jitter through the phase locked loop (PLL) and clock buffers accounts for the majority of skew budgets. We show that taking into account the number of nearly critical paths between clocked elements at each level of the skew hierarchy and variations in the data delays of these paths reduces the difference between global and local skew budgets by more than a factor of two. Another insight is that data path delay variability limits the potential cycle-time benefits of active deskew circuits because the paths with the worst skew are unlikely to also be the paths with the longest data delays.

/pdf/statistical-clock-skew-modeling-with-data-delay-variations-4as6sxl974.pdf

Statistical clock skew modeling with data delay variations

In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as V/sub T/ and I/sub DSS/, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network.

Analysis of the impact of process variations on clock skew

The impact of process fluctuations on the variability of deep sub-micron (DSM) VLSI circuit performances is investigated in this paper. In particular, we show that, as process dimensions scale down in the sub half-micron region, the relative weight of process variability tends to increase, thus wearing down a nonnegligible portion of the benefits that are expected from minimum feature size scaling. Therefore, in order to better exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling, as in the assigned probability technique (APT) (Dal Fabbro et al, Proc. 32nd ACM/IEEE Design Automation Conf., pp. 702-6, 1995). The application of the APT technique to a 16-bit ripple-carry adder designed in 0.35 /spl mu/m, 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies with a power supply ranging from 3.3 V down to 1 V demonstrates how the manufacturability of DSM designs is going to be a vital factor for the successful implementation of high performance or low-power systems in 0.18 /spl mu/m and lesser technologies.

Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep sub-micron CMOS technologies

A new algorithm to determine the number and value of realistic worst-case models for the performance of module library components is presented in this paper. The proposed algorithm employs principal components analysis (PCA) at the performance level to identify the main independent sources of variance for the performance of a set of library modules. Response surfaces methodology (RSM) and propagation of variance (POV) based algorithms are used to efficiently compute the performance level covariance matrix and nonlinear maximum likelihood optimization to trace back worst case models at the SPICE level. The effectiveness of the proposed methodology has been demonstrated by determining a realistic set of worst case models for a 0.25 /spl mu/m CMOS standard cell library.

Realistic worst-case modeling by performance level principal component analysis

The impact of process fluctuations on the variability of Deep Sub-Micron (DSM) VLSI circuits performances is investigated in this paper. In particular we show that, as process dimensions scale down in the sub half-micron region the relative weight of process variability tends to increase, thus wearing down a non negligible portion of the benefits that are expected from minimum feature size scaling. Therefore, in order to betier exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling, as the one described in (I) (APT). The application of the APT technique to a 16-bit ripple-cany adder designed in 0.35~ 0.25~ and 0.18~ CMOS technologies with a power supply ranging &om 3.3V down to 1V will demonstrate how the manufacturability of DSM designs is going to be a vital factor for the successhl implementation of high performance or low-power systems in 0.18pm and lesser technologies.

https://ieeexplore.ieee.org/iel4/5907/15752/00729766.pdf

C. Guardiani

Papers

Analysis of the impact of process variations on clock skew

Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep sub-micron CMOS technologies

Realistic worst-case modeling by performance level principal component analysis

Impact of unrealistic worst case modeling on the technologies perf'orr/iance of vlsi circuits in deep sub-micron cmos