An approach is described for determining the hot-electron-limited voltages for silicon MOSFET's of small dimensions. The approach was followed in determining the room-temperature and the 77 K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 µm. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments. For the 1 µm design considered, the channel hot-electron limits are lower than the substrate hot-electron limits. The maximum voltage, V_{DS} = V_{GS} , is 4.75 V at room temperature (25°C) and 3.5 V at 77 K. More details of the voltage limits as well as the approach for determining them are discussed. Examples of circuits designed with these devices to operate within these hot-electron voltage limits are also discussed.

1 &#181;m MOSFET VLSI technology: Part IV&#8212;Hot-electron design constraints

The ending of optical lithography and the prospects of its successors

1 pm MOSFET VLSI Technology: Part lV— Hot-Electron Design Constraints

This paper describes a double-layer resist-film technique for submicrometer electron-beam lithography. The results of computer simulation and lithography experiments carried out on PMMA/MPR (LO/HI) and MPR/PMMA (HI/LO) double-layer films are reported in full detail. It is shown that an undercut profile suitable for the lift-off processing can be reproducibly obtained by the use of the LO/HI structure over a wide range of electron-beam exposure dose, while the HI/LO structure is of great advantage in the fabrication of lift-off metal gates with a mushroom-like cross section.

Double-layer resist films for submicrometer electron-beam lithography

The increasing complexity of VLSI fabrication often requires the use of multilayer structures above the silicon substrate. Electrical and metallurgical properties of multilayer structures have an important effect on circuit performance and reliability. Although process simulation models are available and widely used for computer-aided process design, none of the existing process simulation programs have the capability for modeling multilayer structures. A new model with such capability has been developed and this paper presents the physics as well as the results of simulation supported by experimental data. The model can simulate many desirable properties of multilayer structures involving polycrystalline silicon, such as grain growth, resistivity and oxidation rate of the polysilicon layer, the impurity redistribution across multilayers after high-temperature thermal processing, impurity segregation both at grain boundaries and at interfaces, and the interdependent phenomena of dopant-dependent oxidation/diffusion.

A process simulation model for multilayer structures involving polycrystalline silicon

An n-channel single-level polysilicon, 25 nm gate-oxide technology, using electron-beam lithography with a minimum feature size of 1 µm, has been implemented for MOSFET logic applications. The six-mask process employs semirecessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques, and reactive ion etching. A description of the process is given, with particular emphasis on topographical considerations. Implementation of a field etchback after source/drain implant to eliminate a low thick-oxide parasitic-device threshold is also discussed.

1 &#181;m MOSFET VLSI technology: Part V&#8212;A single-level polysilicon technology using electron-beam lithography

For pt. IV see ibid., vol.SC14, no.2, p.268 (1979). An n-channel single-level polysilicon, 25 nm gate-oxide technology, using electron-beam lithography with a minimum feature size of 1 /spl mu/m, has been implemented for MOSFET logic applications. The six-mask process employs semirecessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques, and reactive ion etching. A description of the process is given, with particular emphasis on topographical considerations. Implementation of a field etchback after source/drain implant to eliminate a low thick-oxide parasitic-device threshold is also discussed.

1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography

An n-channel silicon gate technology, using electron-beam lithography with minimum dimensions of 1 µm, has been implemented for FET logic applications. The six mask process employs semi-recessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques and reactive ion etching (RIE). A description of the process is given, with particular emphasis or topographical considerations. Implementation of a field etchback after source and drain implant to eliminate a low thick-oxide parasitic device threshold is also discussed.

C.M. Osburn

Papers

1 µm MOSFET VLSI technology: Part V—A single-level polysilicon technology using electron-beam lithography

1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography

One-micrometer electron-beam lithography FET technology

C.M. Osburn

Papers

1 &#181;m MOSFET VLSI technology: Part V&#8212;A single-level polysilicon technology using electron-beam lithography

1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography

One-micrometer electron-beam lithography FET technology

1 µm MOSFET VLSI technology: Part V—A single-level polysilicon technology using electron-beam lithography