C
Carlo Guardiani
Researcher at STMicroelectronics
Publications - 22
Citations - 213
Carlo Guardiani is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Design for manufacturability & Very-large-scale integration. The author has an hindex of 8, co-authored 22 publications receiving 212 citations. Previous affiliations of Carlo Guardiani include PDF Solutions.
Papers
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Proceedings ArticleDOI
Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling
TL;DR: A methodology for hierarchical statistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented and permits the statistical characterization of large analog and mixed-signal systems.
Proceedings ArticleDOI
Manufacturability of low power CMOS technology solutions
A. J. Strojwas,M. Quarantelli,J. Borel,Carlo Guardiani,G. Nicollini,G. Crisenza,B. Franzini,J. Wiart +7 more
TL;DR: This paper discusses manufacturabilty of state-of-the-art low power technologies, reporting the results on two generations of bulk CMOS technologies, triple-well CMOS and Thin Film Silicon on Insulator technologies.
Journal ArticleDOI
Yield optimization of analog ICs using two-step analytic modeling methods
TL;DR: Two innovative methods for statistical design optimization in the design of a CMOS OP-AMP are applied and the derivation of an analytic function representing the yield surface in thedesign parameters space is derived.
Proceedings ArticleDOI
An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard cells
TL;DR: In this paper it is described a technique that allows to determine the worst-case points with an assigned probability value and the results are presented and compared with those obtained by standard methods both at cell and at circuit level showing the considerable benefits of the new method.
Proceedings ArticleDOI
Automatic characterization and modeling of power consumption in static RAMs
TL;DR: An automatic modeling technique is presented in this paper that allows one to build an accurate model of power consumption in embedded memory blocks by automatically splitting those variables that have a discontinuous effect on the power consumption.