This paper presents a novel ultra low-power rail-to-rail comparator which can be suitably used in low-to-medium speed A/D converters. This comparator adopts a preamplifier followed by a dynamic latch structure to achieve fast-decision, high-resolution as well as reduced kick-back noise. A new adaptive power control technique is used to reduce the power consumption of the preamplifier. The circuit is designed and simulated in Global Foundries 65nm CMOS technology. The simulation results have shown that the power consumption of 12-bit comparator is 191.2 nW at the clock frequency of 15 MHz and 0.8 V supply voltage with a delay of 1.17nS.

An ultra low-power rail-to-rail comparator for ADC designs

This paper presents a new ultra-low power double-tail latched comparator suited for biomedical applications. The proposed comparator benefits from a positive feedback to achieve high resolution with low kickback noise. It is shown by time analysis and simulation that the delay time is significantly reduced compared to a conventional double-tail latched comparator. The presented circuit is designed and simulated in 0.18-μm CMOS technology. The post-layout simulation results show that the designed comparator consumes only 1.56 nW power, at 600 mV supply voltage and 100 kHz clock frequency. This amount is 54.35 % of power consumption of a conventional double-tail latched comparator with the same input referred offset of 7.5 mV. Furthermore, the proposed circuit provides a self-neutralization technique which results 8.8 % reduction of kick-back noise in comparison to the conventional latched comparator. The maximum clock frequency of this circuit is 200 MHz at 1 V supply voltage. The proposed circuit has a power-delay product of 0.0172 fJ at 100 kHz clock frequency. The proposed comparator is well designed to operate with supply voltages between 400 mV and 1 V.

Design and analysis of an ultra-low-power double-tail latched comparator for biomedical applications

This paper presents the design and implementation of a rail-to-rail 460-kS/s 10-bit successive approximation register analog-to-digital converter (ADC) for the power-efficient capacitance measurement The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor capacitance-to-voltage (C2V) converter To be compatible to the output of C2V, a bootstrap switch with body effect reduction is adopted to provide the rail-to-rail processing ability The charge redistribution converter is implemented by a single-ended cascaded binary-weighted capacitive digital-to-analog converter (DAC) The total area of the DAC array is not only limited by the matching behavior but also by the noise performance of C2V To relax the settling requirement and improve the power efficiency, self-timing technique is employed which borrows extra half clock period for open-loop settling of preamps The balance between noise and power consumption of dynamic comparator with preamps is also considered The ADC circuit was implemented in 018- $\mu $ m CMOS technology and occupies an active area of 018 $\mathrm{mm}^{2}$  The tested prototype achieves a signal-to-noise-plus-distortion ratio of 54 dB and a spurious-free dynamic range of 68 dB The integral nonlinearity and differential nonlinearity are 05 and 034 least-significant-bit, respectively The total power consumption is 21 $\mu $ W corresponding to 110 fJ/conversion-step figure of merit

Design and Implementation of a Rail-to-Rail 460-kS/s 10-bit SAR ADC for the Power-Efficient Capacitance Measurement

A fully on-chip, low-power and small area CMOS Relaxation Oscillator (ROSC) with voltage integral feedback structure and a new Bandgap Reference voltage (BGR) for accurate oscillation frequency independent of the PVT and comparator's delay variations is presented. The designed circuit uses a new bandgap reference to generate the reference voltage required by relaxation oscillator which allow variations due to voltage and temperature to be compensated. Another merit of this oscillator is that the phase noise at low-offset frequency is suppressed by the voltage integral feedback circuit. The frequency of the relaxation oscillator is determined by the RC response time. Thus, the current and capacitance are controlled by temperature and process compensation circuits to compensate for the frequency variation. The ROSC is implemented in a 0.18µm CMOS technology and its active area is 0.14mm2. The target frequency is 25MHz and current consumption is 22µA, where V DD is 1.8V. The oscillation frequency variation for V DD ranges from 1.4 to 1.9V is 0.2% and for temperature ranges from −40 to 125°C is 0.18%.

A fully on-chip 25MHz PVT-compensation CMOS Relaxation Oscillator

Low-power successive-approximation (SA) analog-to-digital converters (ADCs) are attracting increasing attention these days in biomedical and sensor network applications. The binary search algorithm is one of the basic idea behind how they obtain a binary code representing an analog input. In practice, the imperfectness of analog circuit elements sometimes results in decision errors and decreases the resolution of A/D conversion. Thus, making accurate decisions using imperfect elements is a big challenge. This paper surveys one solution known as non-binary SA with redundancy as well as related topics and its application to state-of-the-art SA ADCs.

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

This paper describes a low-power 25-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The ADC employs a novel low-energy and area-efficient tri-level switching scheme in the DAC. Compared to the conventional SAR ADC, the average switching energy and total capacitance are reduced by 97% and 75%, respectively. Asynchronous design is implemented to eliminate the conventional system clock which is N-time of sampling rate. Furthermore, a delay-based internal clock generator produces a high-speed signal which allows True Single Phase Clock (TSPC) D Flip-flop (DFF) to be used in the low-speed biomedical applications. The ADC can work between 0 to 1 MS/s. The prototype ADC fabricated in UMC 65 nm 1P6M CMOS achieves best performance at 25 kS/s with 50.1 dB SNDR and 55.3 dB SFDR. Operating at 1 V supply and 25 kS/s, the ADC consumes 281 nW and exhibits a FOM of 43.3 fJ/conversion-step. The chip die area is 145 μm × 120 μm.

A 281-nW 43.3 fJ/conversion-step 8-ENOB 25-kS/s asynchronous SAR ADC in 65nm CMOS for biomedical applications

This paper presents a novel charge-redistribution successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed ADC is based on a novel capacitive DAC switching scheme which employs unit capacitors for voltage sampling and charge redistribution. Compared with published capacitive DAC which uses the same unit size capacitor, the proposed DAC needs only 33% of the total switches. The proposed 8-bit SAR-ADC is designed in Global foundries 65nm CMOS process. SPICE simulation results show that the average switching energy can be reduced by more than 60% compared with published design. The simulated power consumption of the capacitive DAC is about 110 nW at 1.0 V power supply and 100KS/s. The simulated average power consumption of the ADC is about 2.8 μW.

A novel low-voltage low-power SAR ADC for biomedical applications

This paper presents a novel switching scheme for an ultra-low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme employs unit capacitors for voltage sampling and charge redistribution. Compared with previously published capacitive DAC which uses the same unit size of capacitor array, the proposed DAC needed only 33% of the total switches. SPICE simulation results show that the average switching energy can be reduced by more than 50%. An 8-bit SAR-ADC using the proposed switch scheme is designed in Global foundries 65nm CMOS process. The power consumption of the capacitive DAC is 160 nW at 1.2V power supply and 100KS/s.

An ultra-low energy capacitive DAC array switching scheme for SAR ADC in biomedical applications

A new highly energy-efficient SAR ADC with capacitor constructed bypass-window structure is proposed for low-power biomedical applications. The proposed structure is able to bypass the first few conversion phases when the input signal is within a pre-defined window, resulting in an overall power reduction of 59% when the input signal has a possibility of 80% to activate the bypass-window function. Meanwhile, this structure maintains symmetry and has good common-mode noise immunity. Extra comparators and external window-reference voltage are not needed in this new structure. This circuit is designed in 40nm 1P6M CMOS technology. Simulation results show that the ADC achieves a Signal-to-Noise-and-Distortion-Ratio (SNDR) of 61.55 dB when it runs at 1V and at a sampling rate of 2-MS/s. The total power consumption is 11.82μW and the Figure-of-Merit (FoM) is 6.1 fJ/conversion-step.

Chao Yuan

Papers

An ultra low-power rail-to-rail comparator for ADC designs

A 281-nW 43.3 fJ/conversion-step 8-ENOB 25-kS/s asynchronous SAR ADC in 65nm CMOS for biomedical applications

A novel low-voltage low-power SAR ADC for biomedical applications

An ultra-low energy capacitive DAC array switching scheme for SAR ADC in biomedical applications

A capacitor constructed bypass window switching scheme for energy-efficient SAR ADC