Proceedings ArticleDOI
A capacitor constructed bypass window switching scheme for energy-efficient SAR ADC
Yao-Ping Liu,Chao Yuan,Yvonne Lam Ying Hung +2 more
- pp 1352-1355
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TLDR
A new highly energy-efficient SAR ADC with capacitor constructed bypass-window structure is proposed for low-power biomedical applications, able to bypass the first few conversion phases when the input signal is within a pre-defined window, resulting in an overall power reduction.Abstract:
A new highly energy-efficient SAR ADC with capacitor constructed bypass-window structure is proposed for low-power biomedical applications. The proposed structure is able to bypass the first few conversion phases when the input signal is within a pre-defined window, resulting in an overall power reduction of 59% when the input signal has a possibility of 80% to activate the bypass-window function. Meanwhile, this structure maintains symmetry and has good common-mode noise immunity. Extra comparators and external window-reference voltage are not needed in this new structure. This circuit is designed in 40nm 1P6M CMOS technology. Simulation results show that the ADC achieves a Signal-to-Noise-and-Distortion-Ratio (SNDR) of 61.55 dB when it runs at 1V and at a sampling rate of 2-MS/s. The total power consumption is 11.82μW and the Figure-of-Merit (FoM) is 6.1 fJ/conversion-step.read more
Citations
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Proceedings ArticleDOI
A 0.5-V 1.28-MS/s 10-bit SAR ADC with switching detect logic
Yu-Wei Cheng,Kea-Tiong Tang +1 more
TL;DR: The proposed switching detect logic can avoid switch power wasted and reduce the impact of capacitor mismatch from the layout parasitic as well as improve the resolution performance of SAR ADC.
Journal ArticleDOI
A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology
TL;DR: An eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process is presented.
Proceedings ArticleDOI
Verilog-A implementation of energy-efficient SAR ADCs for biomedical application
M. Santhanalakshmi,K. Yasoda +1 more
TL;DR: A Verilog-A implementation of three different energy efficient architectures of Successive Approximation Register (SAR) analog-to-digital converter (ADC), which retained the functionality of existing architecture except for a specific input combination where the existing architecture was less accurate.
Book ChapterDOI
Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices: A Survey
TL;DR: The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs), and provides an overview of the WIMDs, and electrophysiological signals.
Proceedings ArticleDOI
Design of a Low-power Single-channel 8-Bit 1.25GSPS SAR ADC
TL;DR: Undergoing algorithm verification with MATLAB, a single-channel 8-bit 1.25GSPS SAR ADC structure is presented and the pre-simulation results with noise show that the core circuit has the ENOB 7.80bits, the power consumption 2.01mW, and the FOM value 6.29fJ/conv-step when operating at very high speed.
References
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Journal ArticleDOI
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
TL;DR: In this paper, a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure is presented.
Proceedings ArticleDOI
An energy-efficient charge recycling approach for a SAR converter with capacitive DAC
TL;DR: A new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC can be reduced by 37% compared to a conventional switching method by splitting the MSB capacitor into b - 1 binary scaled sub-capacitors.
Journal ArticleDOI
Low-energy and area-efficient tri-level switching scheme for SAR ADC
C. Yuan,Yvonne Y. H. Lam +1 more
TL;DR: In this article, a tri-level switching scheme for low-power successive approximation register (SAR) ADC is proposed, which reduces the number of capacitors in the ADC capacitor array by 75% and results in an area-efficient SAR ADC.
Journal ArticleDOI
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications
TL;DR: An energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications is presented and a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window.
Journal ArticleDOI
A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS
TL;DR: An extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) is presented and tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital- to-Analog Converter (DAC) by 1-bit.
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