Proceedings ArticleDOI
A novel low-voltage low-power SAR ADC for biomedical applications
Chao Yuan,Yvonne Y. H. Lam +1 more
- pp 101-104
TLDR
In this paper, a charge-redistribution successive-approximation register (SAR) analog-to-digital converter (ADC-ADC) is proposed, which employs unit capacitors for voltage sampling and charge redistribution.Abstract:
This paper presents a novel charge-redistribution successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed ADC is based on a novel capacitive DAC switching scheme which employs unit capacitors for voltage sampling and charge redistribution. Compared with published capacitive DAC which uses the same unit size capacitor, the proposed DAC needs only 33% of the total switches. The proposed 8-bit SAR-ADC is designed in Global foundries 65nm CMOS process. SPICE simulation results show that the average switching energy can be reduced by more than 60% compared with published design. The simulated power consumption of the capacitive DAC is about 110 nW at 1.0 V power supply and 100KS/s. The simulated average power consumption of the ADC is about 2.8 μW.read more
Citations
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Proceedings ArticleDOI
An ultra low-power rail-to-rail comparator for ADC designs
TL;DR: In this paper, a novel ultra low-power rail-to-rail comparator is presented, which can be suitably used in low to medium speed A/D converters.
Proceedings ArticleDOI
Verilog-A implementation of energy-efficient SAR ADCs for biomedical application
M. Santhanalakshmi,K. Yasoda +1 more
TL;DR: A Verilog-A implementation of three different energy efficient architectures of Successive Approximation Register (SAR) analog-to-digital converter (ADC), which retained the functionality of existing architecture except for a specific input combination where the existing architecture was less accurate.
Proceedings ArticleDOI
A robust to PVT variations low-voltage low-power current mirror
TL;DR: The mirror is designed using transistors in weak-inversion region, which allows operating with reduced supply voltage, and was used in a one-stage fully-differential OTA, for which a gain of 75 dB was achieved.
Proceedings ArticleDOI
Charge sharing non-binary SAR ADC
TL;DR: The optimization method suggests that the non-binary SAR ADC with lower standard deviation DAC capacitance values will show better static performance and the optimization method shows that the static performance improvement trend is in accordance with the proposed optimization method.
Proceedings ArticleDOI
A novel multi-step C-2C DAC architecture
TL;DR: The DAC presented combines a multi-step methodology and a C-2C converter with a lower resolution than the main converter and four switches to produce the desired analog output signal.
References
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Journal ArticleDOI
A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$ W at 1 MS/s
Michiel van Elzakker,Ed van Tuijl,P.F.J. Geraedts,Daniel Schinkel,Eric A.M. Klumperink,Bram Nauta +5 more
TL;DR: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller.
Proceedings ArticleDOI
An energy-efficient charge recycling approach for a SAR converter with capacitive DAC
TL;DR: A new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC can be reduced by 37% compared to a conventional switching method by splitting the MSB capacitor into b - 1 binary scaled sub-capacitors.
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Kickback noise reduction techniques for CMOS latched comparators
P.M. Figueiredo,J.C. Vital +1 more
TL;DR: This brief reviews existing solutions to minimize the kickback noise and proposes two new ones and HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.
Proceedings ArticleDOI
Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters
Jeongsup Lee,In-Cheol Park +1 more
TL;DR: Simulation results show that the proposed capacitor array structure and switching method can reduce the average energy consumed in the capacitor array by 75% and 60% compared to the conventional method and the splitting capacitor method, respectively.
Proceedings ArticleDOI
A low-offset high-speed double-tail dual-rail dynamic latched comparator
HeungJun Jeon,Yong-Bin Kim +1 more
TL;DR: A new dynamic latched comparator which shows lower input-referred latch offset voltage and higher load drivability than the conventional double-tail dynamic comparators.