Cheng-Hao Yu

TL;DR: In this article, an optimized U-shaped trench gate MOSFET with low resistance is proposed, which adds an n-type region, wrapping the p+ shielding region incorporated at the bottom of the trench gate.

Abstract: This paper presents 2-D numerical simulation results of single-event burnout (SEB) in power planar vertical double-diffused MOSFET (VDMOSFET) with localized carrier lifetime control. A low carrier lifetime control region (LCLCR) is introduced to accelerate the recombination rate of the generated holes caused by an ion's impact. The optimal localized range with LCLCR in epitaxial layer has been investigated. The SEB inhibition mechanism with LCLCR is analyzed and discussed. A VDMOSFET with localized LCLCR can operate like a normal VDMOSFET and can have improved SEB performance effectively. In addition, the leakage current density in breakdown characteristics of VDMOSFET is studied based on the variation of carrier lifetime.

TL;DR: In this paper, the simulation results of single-event burnout (SEB) hardening in a power metal-oxide semiconductor field effect transistor U-Shape Metal Oxide Semiconductor Field Effect Transistor (trench-gate MOSFET) are explained.

TL;DR: In this paper, the authors present 2D numerical simulation results of single-event burnout in power UMOSFETs (trench-gate MOSFets) and investigate hardening solutions to SEB such as carrier lifetime reduction, emitter doping decrease, and p+ plug modification.

TL;DR: In this paper, a split-gate resurf stepped oxide (RSO) vertical UMOSFET with p-pillar under the p+ plug region structure is proposed, which can modulate the electric field of the drift region with the splitgate in 3D and simultaneously brings electric field peaks at the sidewall junction between p-pillars and n-drift region.