Power semiconductor devices constitute the heart of modern power electronic apparatus. They are used in power electronic converters in the form of a matrix of on-off switches, and help to convert power from ac-to-dc (rectifier), dc-to-dc (chopper), dc-to-ac (inverter), and ac-to-ac at the same (ac controller) or different frequencies (cycloconverter). The switching mode power conversion gives high efficiency, but the disadvantage is that due to the nonlinearity of switches, harmonics are generated at both the supply and load sides. The switches are not ideal, and they have conduction and turn-on and turn-off switching losses. Converters are widely used in applications such as heating and lighting controls, ac and dc power supplies, electrochemical processes, dc and ac motor drives, static VAR generation, active harmonic filtering, etc. Although the cost of power semiconductor devices in power electronic equipment may hardly exceed 20–30 percent, the total equipment cost and performance may be highly influenced by the characteristics of the devices. An engineer designing equipment must understand the devices and their characteristics thoroughly in order to design efficient, reliable, and cost-effective systems with optimum performance. It is interesting to note that the modern technology evolution in power electronics has generally followed the evolution of power semiconductor devices. The advancement of microelectronics has greatly contributed to the knowledge of power device materials, processing, fabrication, packaging, modeling, and simulation. Today’s power semiconductor devices are almost exclusively based on silicon material and can be classified as follows:

/pdf/power-semiconductor-devices-4pe39n3k1o.pdf

Power Semiconductor Devices

For low-voltage power MOSFETs technology, Field Plate (FP) and Superjunction (SJ) structures have been applied to reduce on-resistance drastically. As one of the approach for the ultimate structure realization, we propose a multiple stepped oxide FP-MOSFET (MSO-FP-MOSFET) that is extremely close to ideal gradient oxide structure. We have validated an optimum device structure by TCAD simulation and achieved lowest on-resistance of 28.5 mΩmm2 at breakdown voltage of 115.2 V. This performance indicates 25 % improvement compared to conventional devices. Moreover, to demonstrate the MSO-FP-MOSFET characteristics for the first time, we present some measurement data of TEG samples.

100 V class multiple stepped oxide field plate trench MOSFET (MSO-FP-MOSFET) aimed to ultimate structure realization

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage ( ${V}_{\textsf {BR}}$ ). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time ( ${T}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off time ( ${T}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss ( ${E}_{\mathbf {SW}}$ ).

An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss

In this paper, we propose an enhanced efficiency 4H-SiC U-shaped trench-gate MOSFET (UMOSFET) structure. The proposed device structure takes an advantage of a p+-polySi/SiC shielded region to reduce the on-state specific resistance. We show that the heterojunction diode formed by the p+-polySi and the n-drift regions improves the body diode effect, and thereby, reduces the reverse recovery charge. Further, we illustrate through simulation results that in comparison with the traditional p+-SiC shielded UMOSFET, the proposed device structure provides a 56.5% improvement in the figure of merit (including the breakdown voltage and on-resistance), and a 35.7% and 55.5% reduction in specific on-resistance and reverse recovery charge, respectively.

Simulation Study of 4H-SiC UMOSFET Structure With p + -polySi/SiC Shielded Region

Superjunction has arguably been the most creative and important concept in power device field Superjunction vertical diffused MOSFET (SJ VDMOS) has been commercialized and the research effort to l

A Review of Superjunction Vertical Diffused MOSFET

Gate enhanced power UMOSFET (GE-UMOS) is proposed to decrease the specific on -resistance of the device. The key feature of this structure is that the deep trench polysilicon electrode is contacted to the gate electrode, maintaining the breakdown voltage and forming the high electron current density at side n-drift region, thus resulting in a lower on -resistance compared to the superjunction structure and gradient oxide-bypassed (GOB) structure. Furthermore, the performance of GE-UMOS is proved by comparing with the GOB-UMOS structure.

Gate Enhanced Power UMOSFET With Ultralow On-Resistance

An optimized gate-enhanced (GE) power UMOSFET with split gate (SGE-UMOS) is proposed. This device shows the reduction in specific on-state resistance (Rsp) at a breakdown voltage of 119 V as compared to the gradient oxide-bypassed (GOB) UMOS and GE-UMOS devices, which is due to the higher N-type concentration in the drift region. In addition, the split-gate floating structure in SGE-UMOS also reduces the gate-source electrode parasitic capacitor. The numerical simulation results indicate that the proposed device features high performance with improved Rsp and Qg as compared to that of the GOB-UMOS and GE-UMOS devices.

High-Performance Gate-Enhanced Power UMOSFET With Optimized Structure

An optimized split-gate-enhanced UMOSFET (SGE-UMOS) layout design is proposed, and its mechanism is investigated by 2-D and 3-D simulations. The layout features trench surrounding mesa (TSM): First, it optimizes the distribution of electric field density in the outer active mesa, reduces the electric-field crowding effect, and improves the breakdown voltage of the SGE-UMOS device. Second, it is unnecessary to design the layout corner with a large diameter in the termination region for the TSM structure as the conventional mesa surrounding trench (MST) structure, which is more efficient in terms of silicon usage. Rsp.on is reduced when compared with the MST structure within the same rectangular chip area. The BV of SGE-UMOS is increased from 72 to 115 V, and Rsp.on is reduced by approximately 3.5% as compared with the MST structure, due to the application of the TSM. Finally, it needs five masks in the process, and the trenches in active and termination regions are formed with the same processing steps; hence, the manufacturing process is simplified, and the cost is reduced as well.

Split-Gate-Enhanced UMOSFET With an Optimized Layout of Trench Surrounding Mesa

In this paper, a split-gate resurf stepped oxide (RSO) vertical UMOSFET with p-pillar under the p+ plug region structure is proposed. The p-pillar could modulate the electric field of the drift region with the split-gate in 3-D and simultaneously brings electric field peaks at the sidewall junction between p-pillar and n-drift region. Thus the split-gate enhanced with p-pillar (SGEP) UMOS could increase the drift region doping concentration, reduce the on-state-specific resistance, and maintains the breakdown voltage as compared with the super junction and split-gate RSO UMOSs. Numerical simulation results show that the charge imbalance endurance of SGEP is also largely increased.

High-Performance Split-Gate Enhanced UMOSFET With p-Pillar Structure

The feasibility study of semifloating gate (SFG) transistor dosimeter consisting a large area p-i-n diode between floating gate and drain region is described. No bias is applied during irradiation. The SFG is charged via the diode when exposed to gamma rays, and reset with the diode positively biased. A comprehensive device simulation that includes the mechanism of charge collection, the operation of device’s threshold voltage ( $V$ th) reading, and the effect of diode dark current have been carried out with sentaurus TCAD. As a result, high linear dependence of the $V$ th on the absorbed dose of ionizing radiation is observed with a sensitivity of 65.8 mV/Gy, which suggests that this device could be used as a sensitive gamma-ray dosimeter.

Hai-fan Hu

Papers

Gate Enhanced Power UMOSFET With Ultralow On-Resistance

High-Performance Gate-Enhanced Power UMOSFET With Optimized Structure

Split-Gate-Enhanced UMOSFET With an Optimized Layout of Trench Surrounding Mesa

High-Performance Split-Gate Enhanced UMOSFET With p-Pillar Structure

Feasibility Study of Semifloating Gate Transistor Gamma-Ray Dosimeter