Progress in 2D photonic crystal Fano resonance photonics

Flexible electronics has significantly advanced over the last few years, as devices and circuits from nanoscale structures to printed thin films have started to appear. Simultaneously, the demand for high-performance electronics has also increased because flexible and compact integrated circuits are needed to obtain fully flexible electronic systems. It is challenging to obtain flexible and compact integrated circuits as the silicon based CMOS electronics, which is currently the industry standard for high-performance, is planar and the brittle nature of silicon makes bendability difficult. For this reason, the ultra-thin chips from silicon is gaining interest. This review provides an in-depth analysis of various approaches for obtaining ultra-thin chips from rigid silicon wafer. The comprehensive study presented here includes analysis of ultra-thin chips properties such as the electrical, thermal, optical and mechanical properties, stress modelling, and packaging techniques. The underpinning advances in areas such as sensing, computing, data storage, and energy have been discussed along with several emerging applications (e.g., wearable systems, m-Health, smart cities and Internet of Things etc.) they will enable. This paper is targeted to the readers working in the field of integrated circuits on thin and bendable silicon; but it can be of broad interest to everyone working in the field of flexible electronics.

/pdf/ultra-thin-chips-for-high-performance-flexible-electronics-2vmyrzfqsj.pdf

Ultra-thin chips for high-performance flexible electronics

In the last two decades, several new concepts for improving the performance of infrared detectors have been proposed. These new concepts particularly address the drive towards the so-called high operating temperature focal plane arrays (FPAs), aiming to increase detector operating temperatures, and as a consequence reduce the cost of infrared systems. In imaging systems with the above megapixel formats, pixel dimension plays a crucial role in determining critical system attributes such as system size, weight and power consumption (SWaP). The advent of smaller pixels has also resulted in the superior spatial and temperature resolution of these systems. Optimum pixel dimensions are limited by diffraction effects from the aperture, and are in turn wavelength-dependent. In this paper, the key challenges in realizing optimum pixel dimensions in FPA design including dark current, pixel hybridization, pixel delineation, and unit cell readout capacity are outlined to achieve a sufficiently adequate modulation transfer function for the ultra-small pitches involved. Both photon and thermal detectors have been considered. Concerning infrared photon detectors, the trade-offs between two types of competing technology-HgCdTe material systems and III-V materials (mainly barrier detectors)-have been investigated.

http://iopscience.iop.org/article/10.1088/0034-4885/79/4/046501/pdf

Challenges of small-pixel infrared detectors: a review

Neuromorphic engineering (NE) encompasses a diverse range of approaches to information processing that are inspired by neurobiological systems, and this feature distinguishes neuromorphic systems from conventional computing systems. The brain has evolved over billions of years to solve difficult engineering problems by using efficient, parallel, low-power computation. The goal of NE is to design systems capable of brain-like computation. Numerous large-scale neuromorphic projects have emerged recently. This interdisciplinary field was listed among the top 10 technology breakthroughs of 2014 by the MIT Technology Review and among the top 10 emerging technologies of 2015 by the World Economic Forum. NE has two-way goals: one, a scientific goal to understand the computational properties of biological neural systems by using models implemented in integrated circuits (ICs); second, an engineering goal to exploit the known properties of biological systems to design and implement efficient devices for engineering applications. Building hardware neural emulators can be extremely useful for simulating large-scale neural models to explain how intelligent behavior arises in the brain. The principal advantages of neuromorphic emulators are that they are highly energy efficient, parallel and distributed, and require a small silicon area. Thus, compared to conventional CPUs, these neuromorphic emulators are beneficial in many engineering applications such as for the porting of deep learning algorithms for various recognitions tasks. In this review article, we describe some of the most significant neuromorphic spiking emulators, compare the different architectures and approaches used by them, illustrate their advantages and drawbacks, and highlight the capabilities that each can deliver to neural modelers. This article focuses on the discussion of large-scale emulators and is a continuation of a previous review of various neural and synapse circuits (Indiveri et al., 2011). We also explore applications where these emulators have been used and discuss some of their promising future applications.

/pdf/large-scale-neuromorphic-spiking-array-processors-a-quest-to-3r2jgke1zt.pdf

Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain

We have successfully mass-produced novel stacked back-illuminated CMOS image sensors (BI-CIS). In the new CIS, we introduced advanced Cu2Cu hybrid bonding that we had developed. The electrical test results showed that our highly robust Cu2Cu hybrid bonding achieved remarkable connectivity and reliability. The performance of image sensor was also investigated and our novel stacked BI-CIS showed favorable results.

Novel stacked CMOS image sensor with advanced Cu2Cu hybrid bonding

Wafer-level bonding/stacking technology for 3D integration

https://ir.nctu.edu.tw:443/bitstream/11536/15218/1/000300190600002.pdf

Low temperature bonding technology for 3D integration

https://ir.nctu.edu.tw:443/bitstream/11536/21288/1/000314258600003.pdf

Reliability of key technologies in 3D integration

https://ir.nctu.edu.tw:443/bitstream/11536/15220/1/000300190600009.pdf

BCB-to-oxide bonding technology for 3D integration

Bonding temperature optimization of SU-8 material for metal/adhesive hybrid bonding was investigated The good bond quality of SU-8 adhesive can be achieved with the bonding temperature between 150 degrees C and 250 degrees C, while bond failures of SU-8 wafers are observed starting from 275 degrees C IR transmittance spectra measurements indicate the crosslinks inside SU-8 break and further bond failure is observed due to the large decomposition of epoxy rings and phenyl in plane bending above 275 degrees C This research provides guidelines of material selection and bonding parameters for heterogeneous integration, 3DIC and MEMS applications using metal/adhesive hybrid bonding

Cheng Ta Ko

Papers

Wafer-level bonding/stacking technology for 3D integration

Low temperature bonding technology for 3D integration

Reliability of key technologies in 3D integration

BCB-to-oxide bonding technology for 3D integration

Bonding temperature optimization and property evolution of SU-8 material in metal/adhesive hybrid wafer bonding.