Showing papers by "Chih-Kong Ken Yang published in 2008"
TL;DR: A new adaptation strategy of I/O link equalizers is presented based on minimizing the bit error rate (BER) as the objective function to maximize the receiver voltage margin and requires almost no additional hardware compared to SS-LMS adaptation.
Abstract: A new adaptation strategy of I/O link equalizers is presented based on minimizing the bit error rate (BER) as the objective function to maximize the receiver voltage margin. The adaptation strategy is verified in a 90-nm test chip on both the transmitter finite-impulse response filter (Tx-FIR) and the receiver decision-feedback equalizer (Rx-DFE). The performance is compared with the commonly used sign-sign least mean square (SS-LMS) adaptation and demonstrates significant improvements especially in the case of the Tx-FIR. This paper also demonstrates that in a highly attenuating system that contains both a Tx-FIR and Rx-DFE, using a Tx-FIR subject to peak output power constraint to compensate pre-cursor ISI is worse than solely using an Rx-DFE. The adaptation strategy is further applied to adapt the sampling phase of the clock-and-data recovery loop (CDR). The technique enables near-optimal BER performance by substantially reducing the pre-cursor ISI and requires almost no additional hardware compared to SS-LMS adaptation.
52 citations
TL;DR: This work proposes a forward FIR equalizer and a decision-feedback equalizer (DFE) that compensate for both data and edge samples that achieve convergence.
Abstract: Limited channel bandwidth introduces inter-symbol interference (ISI) at both data and edge samples. In addition to the ISI at data samples, ISI at the edge samples (edge ISI) increases the bit error rate (BER) by degrading on the eye diagram and increasing the jitter of the clock and data recovery (CDR). This work proposes a forward FIR equalizer and a decision-feedback equalizer (DFE) that compensate for both data and edge samples. To adapt both the data and edge equalizers, a modified LMS adaptation algorithm is introduced to achieve convergence. A transmitter and receiver are implemented in 0.13 mum and 0.18 mum technologies respectively. The edge ISI is improved by 20% and the jitter is improved by 10% in measurement. The link operates over a 120'' FR4 channel with 24 dB attenuation at Nyquist frequency, and the BER is below 10-14 at 3.6 Gb/s.
47 citations
TL;DR: A comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high- speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model.
Abstract: MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional RC delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general RC delay model format. Theoretical results are compared with Spice simulations in a 0.13-mum CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple RC delay model fails to provide.
37 citations
17 Nov 2008
TL;DR: A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage and more than 4.5times of reduction in the power consumption is achieved.
Abstract: A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques. The proposed CMOS ring oscillator is designed and implemented with a charge-pump based phase-locked loop in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 4-GHz output clock is reduced from 10.66-ps to 5.04-ps while subject to switching noise with magnitude of 2.5% of the supply voltage at 150-MHz. Furthermore, more than 4.5times of reduction in the power consumption is achieved.
9 citations
18 Jun 2008
TL;DR: In this article, the authors demonstrate a technique that embeds a resonant interpolator into the clock buffer to correct the phase error without additional buffer elements, and measure the measured DNL of the interpolator is < 0.6 LSB even with quadrature inputs and phase error < 1 ps is achieved.
Abstract: Large static phase errors result from injection-locked LC clock buffers due to slight frequency mismatch between the input frequency and the tankpsilas resonant frequency. The paper demonstrates a technique that embeds a resonant interpolator into the clock buffer to correct the phase error without additional buffer elements. The test chip is fabricated in a 0.13 mum digital CMOS technology. Measured DNL of the resonant interpolator is <0.6 LSB even with quadrature inputs and phase error <1 ps is achieved.
7 citations