D
D. Lattard
Researcher at University of Paris
Publications - 5
Citations - 117
D. Lattard is an academic researcher from University of Paris. The author has contributed to research in topics: Chip & Synchronous CDMA. The author has an hindex of 3, co-authored 5 publications receiving 103 citations.
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Proceedings ArticleDOI
A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip
D. Lattard,Edith Beigne,Christian Bernard,C. Bour,Fabien Clermidy,Yves Durand,J. Durupt,Didier Varreau,P. Vivet,P. Penard,A. Bouttier,F. Berens +11 more
TL;DR: The FAUST chip integrates a baseband processing architecture in which communications between IPs are supported by an asynchronous network-on-chip (NoC) structure that facilitates physical implementation and power management.
Proceedings ArticleDOI
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters
Pascal Vivet,Eric Guthmuller,Yvain Thonnart,Gael Pillonnet,Guillaume Moritz,Ivan Miro-Panades,Cesar Fuguet,J. Durupt,Christian Bernard,Didier Varreau,Julian Pontes,Sebastien Thuries,David Coriat,Michel Harrand,Denis Dutoit,D. Lattard,Lucile Arnaud,Jean Charbonnier,Perceval Coudrain,Arnaud Garnier,Frédéric Berger,Alain Gueugnot,Alain Greiner,Quentin L. Meunier,Alexis Farcy,Alexandre Arriordaz,Severine Cheramy,Fabien Clermidy +27 more
TL;DR: An active interposer integrating a Switched Capacitor Voltage Regulator (SCVR) for on-chip power management, flexible system interconnect topologies between all chiplets for scalable cache coherency support, and energy-efficient 3D-plugs for dense inter-layer communication is presented.
Proceedings ArticleDOI
Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes
TL;DR: This paper extended some simple DFS architectures based on GALS architectures in 130nm technology to fine-grain Dynamic Voltage and Frequency Scaling architectures to reduce dynamic and static power reduction at 65 nm node.
Proceedings ArticleDOI
ICARE, VICASSO, ACCELAN, MUSYCA: an innovative family of DSSS/CDMA ASICs for implementing DSSS/CDMA transceivers
Jean-Rene Lequepeys,Laurent Ouvry,M. Des Noes,D. Lattard,Didier Varreau,N. Daniele,B. Piaget,D. Noguet,Marc Laugeois,R. Lionti +9 more
TL;DR: In this article, the authors describe two ASICs (ICARE and VICASSO) based on co-channel interference cancellation (IC) schemes, which meanwhile have better performance than conventional detectors and are particularly attractive for hardware implementation.
Proceedings ArticleDOI
MUSYCA: a quasi synchronous CDMA VLSI processor and its application to multiple access
TL;DR: An implementation of a QS-CDMA digital processor is proposed along with a test platform and performances evaluation, which offers a great flexibility due to its high programmability and an application to the uplink of a cable modem is proposed.