D
Denis Dutoit
Researcher at University of Grenoble
Publications - 26
Citations - 638
Denis Dutoit is an academic researcher from University of Grenoble. The author has contributed to research in topics: Interposer & Clock signal. The author has an hindex of 12, co-authored 25 publications receiving 532 citations. Previous affiliations of Denis Dutoit include STMicroelectronics.
Papers
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Proceedings ArticleDOI
Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications
Diego Melpignano,Luca Benini,Eric Flamand,Bruno Jego,Thierry Lepley,Germain Haugou,Fabien Clermidy,Denis Dutoit +7 more
TL;DR: P2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters, and a dedicated version of the OpenCV vision library is provided in the P2012 SW Development Kit to enable visual analytics acceleration.
Proceedings Article
A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC
Denis Dutoit,Christian Bernard,Severine Cheramy,Fabien Clermidy,Yvain Thonnart,Pascal Vivet,Christian Freund,Vincent Guerin,Stéphane Guilhot,Stephane Lecomte,Gianni Qualizza,Julien Pruvost,Yves Dodo,Nicolas Hotelier,Jean Michailos +14 more
TL;DR: Measurements of the 3D-IC show that the targeted 12.8 GByte/s bandwidth is achieved in worst case conditions, while offering a 0.9 pJ/bit 3D I/O link power efficiency.
Proceedings ArticleDOI
EUROSERVER: Energy Efficient Node for European Micro-Servers
Yves Durand,Paul M. Carpenter,Stefano Adami,Angelos Bilas,Denis Dutoit,Alexis Farcy,Georgi Gaydadjiev,John Goodacre,Manolis Katevenis,Manolis Marazakis,Emil Matus,Iakovos Mavroidis,John Thomson +12 more
TL;DR: The EUROSERVER device will embed multiple silicon "chiplets" on an active silicon interposer, which is pioneering a system architecture approach that allows specialized silicon devices to be built even for low-volume markets where NRE costs are currently prohibitive.
Proceedings ArticleDOI
Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures
P. Coudrain,Jean Charbonnier,Arnaud Garnier,Pascal Vivet,Remi Velard,Andrea Vinci,F. Ponthenier,Alexis Farcy,Roselyne Segaud,P. Chausse,Lucile Arnaud,Didier Lattard,Eric Guthmuller,Giovanni Romano,Alain Gueugnot,Frédéric Berger,Jerome Beltritti,Therry Mourier,Mathilde Gottardi,Stephane Minoret,C. Ribiere,Gilles Romero,Pierre-Emile Philip,Yorrick Exbrayat,Daniel Scevola,Didier Campos,Maxime Argoud,Nacima Allouti,Raphael Eleouet,Cesar Fuguet Tortolero,Christophe Aumont,Denis Dutoit,Corinne Legalland,Jean Michailos,Severine Cheramy,Gilles Simon +35 more
TL;DR: The first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested is reported.
Journal ArticleDOI
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
Pascal Vivet,Eric Guthmuller,Yvain Thonnart,Gael Pillonnet,Cesar Fuguet,Ivan Miro-Panades,Guillaume Moritz,J. Durupt,Christian Bernard,Didier Varreau,Julian Pontes,Sebastien Thuries,David Coriat,Michel Harrand,Denis Dutoit,Didier Lattard,Lucile Arnaud,Jean Charbonnier,P. Coudrain,Arnaud Garnier,Frédéric Berger,Alain Gueugnot,Alain Greiner,Quentin L. Meunier,Alexis Farcy,Alexandre Arriordaz,Severine Cheramy,Fabien Clermidy +27 more
TL;DR: The IntAct project as mentioned in this paper integrates six chiplets in FDSOI 28-nm technology, which are 3D-stacked onto this active interposer in 65-nm process, offering a total of 96 computing cores.