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Eric Guthmuller
Researcher at University of Grenoble
Publications - 22
Citations - 217
Eric Guthmuller is an academic researcher from University of Grenoble. The author has contributed to research in topics: Cache & Cache pollution. The author has an hindex of 7, co-authored 21 publications receiving 135 citations. Previous affiliations of Eric Guthmuller include Alternatives & French Alternative Energies and Atomic Energy Commission.
Papers
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Proceedings ArticleDOI
Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures
P. Coudrain,Jean Charbonnier,Arnaud Garnier,Pascal Vivet,Remi Velard,Andrea Vinci,F. Ponthenier,Alexis Farcy,Roselyne Segaud,P. Chausse,Lucile Arnaud,Didier Lattard,Eric Guthmuller,Giovanni Romano,Alain Gueugnot,Frédéric Berger,Jerome Beltritti,Therry Mourier,Mathilde Gottardi,Stephane Minoret,C. Ribiere,Gilles Romero,Pierre-Emile Philip,Yorrick Exbrayat,Daniel Scevola,Didier Campos,Maxime Argoud,Nacima Allouti,Raphael Eleouet,Cesar Fuguet Tortolero,Christophe Aumont,Denis Dutoit,Corinne Legalland,Jean Michailos,Severine Cheramy,Gilles Simon +35 more
TL;DR: The first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested is reported.
Journal ArticleDOI
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
Pascal Vivet,Eric Guthmuller,Yvain Thonnart,Gael Pillonnet,Cesar Fuguet,Ivan Miro-Panades,Guillaume Moritz,J. Durupt,Christian Bernard,Didier Varreau,Julian Pontes,Sebastien Thuries,David Coriat,Michel Harrand,Denis Dutoit,Didier Lattard,Lucile Arnaud,Jean Charbonnier,P. Coudrain,Arnaud Garnier,Frédéric Berger,Alain Gueugnot,Alain Greiner,Quentin L. Meunier,Alexis Farcy,Alexandre Arriordaz,Severine Cheramy,Fabien Clermidy +27 more
TL;DR: The IntAct project as mentioned in this paper integrates six chiplets in FDSOI 28-nm technology, which are 3D-stacked onto this active interposer in 65-nm process, offering a total of 96 computing cores.
Proceedings ArticleDOI
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters
Pascal Vivet,Eric Guthmuller,Yvain Thonnart,Gael Pillonnet,Guillaume Moritz,Ivan Miro-Panades,Cesar Fuguet,J. Durupt,Christian Bernard,Didier Varreau,Julian Pontes,Sebastien Thuries,David Coriat,Michel Harrand,Denis Dutoit,D. Lattard,Lucile Arnaud,Jean Charbonnier,Perceval Coudrain,Arnaud Garnier,Frédéric Berger,Alain Gueugnot,Alain Greiner,Quentin L. Meunier,Alexis Farcy,Alexandre Arriordaz,Severine Cheramy,Fabien Clermidy +27 more
TL;DR: An active interposer integrating a Switched Capacitor Voltage Regulator (SCVR) for on-chip power management, flexible system interconnect topologies between all chiplets for scalable cache coherency support, and energy-efficient 3D-plugs for dense inter-layer communication is presented.
Proceedings ArticleDOI
3D advanced integration technology for heterogeneous systems
Pascal Vivet,Christian Bernard,Fabien Clermidy,Denis Dutoit,Eric Guthmuller,Ivan-Miro Panades,Gael Pillonnet,Yvain Thonnart,Arnaud Garnier,Didier Lattard,A. Jouve,Franck Bana,Thierry Mourier,Severine Cheramy +13 more
TL;DR: A short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description.
Proceedings ArticleDOI
Adaptive Stackable 3D Cache Architecture for Manycores
TL;DR: This paper presents an adaptive 3Dcache architecture taking advantage of dense vertical connections in stacked chips and proposes a dynamically adaptive mechanism to optimize the use of the aforementioned 3D cache architecture according to the workload needs.