Berkeley reliability tools (BERT) simulates the circuit degradation (drift) due to hot-electron degradation in MOSFETs and bipolar transistors and predicts circuit failure rates due to oxide breakdown and electromigration in CMOS, bipolar, and BiCMOS circuits. With the increasing importance of reliability in today's and future technology, a reliability simulator such as this is expected to serve as the engine of design-for-reliability in a building-in-reliability paradigm. BERT works in conjunction with a circuit simulator such as SPICE in order to simulate reliability for actual circuits, and, like SPICE, acts as an interactive tool for design. BERT is introduced and the current work being done is summarized. BERT is used to study the reliability of a BiCMOS inverter chain, and performance data are presented. >

Berkeley reliability tools-BERT

In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffers, and each places a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are presented for propagation delay and power dissipation, as well as a new split-capacitor model of hot-carrier reliability of tapered buffers and a two-component physical area model. Each performance criterion is individually investigated and analyzed with respect to the number of stages and tapering factor, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. The creation of process dependent look-up tables for optimal buffer design is described, and a methodology to apply these look-up tables to application-specific tapered buffers for both unconstrained and constrained systems is developed. >

A unified design methodology for CMOS tapered buffers

A review of hot-carrier degradation mechanisms in MOSFETs

The positive bias temperature instability (PBTI) of submicron MOSFETs has been investigated. It is found that the PBTI can be as large as the well-known negative bias temperature instability (NBTI). While the NBTI includes both Interface state generation and positive charge formation in the gate oxide, the PBTI only exists in the form of donor-like interface state generation. These donor-like interface states are localized symmetrically near the source and drain junctions and are negligible in the middle of the channel. Their dependence on the stressing electrical field strength and temperature is investigated and an activation energy of 1.23 eV is extracted. The PBTI creation follows the first order kinetics and the final saturation level is fixed by the number of defects available in the device. The experimental results show that the water- and boron-related species are two necessary reactants of the electrochemical reaction leading to the PBTI. Some speculation on the PBTI formation process is included.

Positive bias temperature instability in MOSFETs

The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F) and the transistor aspect ratio (/spl tau/) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability.

Design considerations for CMOS digital circuits with improved hot-carrier reliability

For pt.I, see ibid., vol.38 no.8, pp.1852-1858, Aug. 1991. The physical effects discussed in Pt.I are classified with respect to real operation of devices in circuits from an engineer's viewpoint. Stress results from different kinds of logic stages are discussed and relations set up between static and dynamic lifetimes. It is shown that within certain limited error boundaries, the static approach is essentially valid as long as stress conditions are considered that are oriented to operation in digital logic. The transmission gate is investigated separately, because in this case specific phenomena caused by bidirectional stress must be considered. >

Dynamic degradation in MOSFET's. II. Application in the circuit environment

Capacitance-voltage measurements were performed on small-size MOSFET's with applied drain voltage to obtain information about hot-electron effects. The theoretical analysis shows that hot carriers cause remarkable changes 1) in the vertical and horizontal distribution of the electrons in the inversion layer, 2) in the surface potential drop, 3) in the depletion charge, and 4) in the effective threshold voltage. The influence of these hot-electron effects on the channel current is discussed.

D. Schmitt-Landsiedel

Papers

Dynamic degradation in MOSFET's. II. Application in the circuit environment

Novel hot-electron effects in the channel of MOSFET's observed by capacitance measurements