Daniel Connelly

TL;DR: In this article, the performance of an evolutionary FinFET design (iFinFET) is benchmarked against that of the conventional bulk Fin-FET and stacked-nanowire gate-all-around (GAA) FET, through 3D device simulations, for both n-channel and p-channel transistors.

TL;DR: In this paper, the electrostatic benefit of using a silicon-on-insulator (SOI) wafer substrate versus a bulk-silicon substrate with optimized supersteep retrograde (SSR) doping for a low-power 7-/8-nm FinFET technology was investigated via 3D device simulations and a fitted compact model to estimate the manufacturing yield of six-transistor SRAM cells.

TL;DR: In this paper, the benefits of a super-steep retrograde (SSR) fin doping profile, which can be achieved using the oxygen insertion technology, are quantified via 3-D technology computer-aided design simulations for the 7/8-nm bulk-Si FinFET technology targeting low-power applications.

TL;DR: The results show that the iFinFET is a promising candidate for future low-power system-on-chip applications, providing superior electrostatic integrity relative to the FinFET without the additional process complexity and substantial gate capacitance penalty of the GAA FET.

TL;DR: 3-D technology computer-aided design simulations show that the theoretical limit of BV for LDMOS can be surpassed and Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology.