Showing papers by "David A. Johns published in 1995"

Comparison of DC offset effects in four LMS adaptive algorithms

Abstract: It is well known that DC offsets degrade the performance of analog adaptive filters. In this paper, the effects of DC offsets on four variations of the stochastic gradient algorithm are analyzed. Assuming a Gaussian probability distribution for the input signal and error signal, the output mean squared error (MSE) performance in the presence of DC offsets is evaluated for each of the algorithms. The theoretical work is compared with computer simulations and the results, together with convergence properties of each of the algorithms and their respective hardware requirements, are used in selecting the most appropriate algorithm. Although a Gaussian input distribution is assumed, it may reasonably be inferred that the critical results obtained should also hold for other input distributions. >

A 100 Mb/s BiCMOS adaptive pulse-shaping filter

Abstract: With the growing demand for high-speed transmission of digital data, there is a challenge for utilizing the existing copper plant as the transmission medium, especially for short-hop links. This medium offers a lower cost to a fiber medium, but requires more sophisticated electronics to account for electromagnetic emissions, cross-talk, and cable loss. These include pulse shaping filters, cross-talk cancelers, and equalizers. To maintain system cost at a minimum, analog solutions are preferred. A continuous-time tunable biquad implemented in a 0.8 /spl mu/m BiCMOS process and configured as an adaptive pulse-shaping filter is described. The biquad is tunable over the range 10-230 MHz with variable Q factors. It is composed of five transconductance-C integrators each dissipating a static power of 10 mW at 5 V. A method for adapting the filter's pole-frequency and Q-factor while servicing 100 Mb/s NRZ data is presented together with experimental results.

A 200 MHz 3.3 V BiCMOS class-IV partial-response analog Viterbi decoder

Abstract: Analog Viterbi decoders have recently been shown to be viable alternatives to digital implementations. In fact a commercial realization for a class-IV partial-response maximum-likelihood magnetic read-channel has been reported. Analog Viterbi decoders offer the advantages of reduced power and size primarily due to the elimination of the A/D converter required in digital implementations. The analog Viterbi decoder described here offers the advantages of less complexity and improved robustness to circuit imperfections as compared to previously-reported realizations. This decoder was fabricated in a 0.8 /spl mu/m BiCMOS process, consumes 30 mW from a 3.3V power supply while operating at an effective rate of 200 MSymbols/s, and has a core area of only 0.5 mm/sup 2/.

Analysis of /spl Delta//spl Sigma/ modulators with zero mean stochastic inputs

Abstract: In this paper, a new framework for the analysis of /spl Delta//spl Sigma/ modulators with stochastic inputs is proposed. The framework is based on assuming that the input to the one-hit quantizer is a Gaussian random process with zero mean and is thus able to interrelate the autocorrelation and cross-correlation of different signals of the modulator. Two main equations describing the behavior of two different /spl Delta//spl Sigma/ topologies are derived. These two equations are generally nonlinear and can be of arbitrary order, hence approximations are used to study some interesting cases. First, the nonlinear equations are linearized and solved analytically for first-order modulator with white inputs and numerically for colored inputs both with and without dithering. Also, a numerical iterative approach is used for second and fourth order modulators with white and colored inputs. In these cases, the variance of the one-bit quantizer input is found as a function of modulator input power. Next, the variance of the one-bit quantizer input is calculated when large amplitude oscillations are present assuming a large amplitude limit cycle to have a sinusoidal autocorrelation. Finally, an attempt is made to estimate the modulator's critical input power level beyond which these large amplitude limit cycles start. >

An approach for tuning high-Q continuous-time bandpass filters

Abstract: A new technique for tuning high-Q continuous-time filters is presented. This technique is a modified version of an adaptive tuning method where the tuning signals are sinusoids generated by digital bandpass delta sigma oscillators. As will be shown, the required building blocks for the tuning system are simple. Simulation results are presented to show the feasibility of the proposed approach.

2 V fully-differential SC integrator in standard CMOS

Abstract: A 2 V fully-differential SC integrator is developed for a standard double-poly CMOS without the need for clock or supply-voltage multiplication. The common mode at the integrator output is set to maximise the signal swing, and the common mode at the input to the OTA is set at the negative rail, maximising the overdrive on all the switches. Two capacitive common-mode adjustment networks are required to alleviate large leakage currents associated with parasitic junction diodes. A novel CMFB technique is proposed. Simulation results are presented for a 1.2 /spl mu/m CMOS process.