Showing papers by "David A. Johns published in 2008"
TL;DR: A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented and validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 CMOS process.
Abstract: A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 104 clock cycles.
92 citations
18 Nov 2008
TL;DR: A 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 mum CMOS technology is demonstrated, which is less than half of that required by the feedback topology.
Abstract: A 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth is implemented in 0.18 mum CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0-3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).
43 citations
TL;DR: A pipelined ADC architecture for use in sub-sampled systems which is power scalable in relation to its down sampled bandwidth is presented and a technique to eliminate the front-end sample hold, thereby reducing power consumption is presented.
Abstract: A pipelined ADC architecture for use in sub-sampled systems which is power scalable in relation to its down sampled bandwidth is presented. The ADC uses a technique to eliminate the front-end sample hold, thereby reducing power consumption. The technique allows for a power savings of 20% compared to a previous design. A method to improve the settling behavior of rapid power-on opamps is also presented. Measured results in a 1.8 V 0.18 CMOS process verify the removal of the front-end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With 50 MS/s, for the SNDR is 51.5 dB, and with 4.55 MS/s for the SNDR is 52.2 dB.
35 citations
TL;DR: It is found that finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the architecture.
Abstract: In this brief, single-path time-interleaved delta-sigma modulators are analyzed and evaluated. It is found that finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the architecture. A hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators is proposed to mitigate the mismatch problem.
12 citations
18 Nov 2008
TL;DR: A technique to improve power scaling efficiency of MEMS interfaces over previous approaches is presented by cascading gain stages through an input gain-select mux, and power scaling with respect to input bandwidth of the sensor is achieved through periodic power-down of the interface.
Abstract: A technique to improve power scaling efficiency of MEMS interfaces over previous approaches is presented. Power scaling with respect to amplitude is achieved by cascading gain stages through an input gain-select mux, and power scaling with respect to input bandwidth of the sensor is achieved through periodic power-down of the interface. A prototype of the interface was fabricated in 1.8V , 0.18 mum CMOS process. Its power consumption scales between 4 muW -5.33 mW, while maintaining an SFDR of approx. 80 dB, a THD of 78 dB, and an input referred noise of 170.0nV/radicHz.
5 citations
TL;DR: A low-complexity signaling scheme that can achieve 3-5-dB coding gain over uncoded four-level pulse amplitude modulation (PAM) and is designed and implemented in a 0.18-mum standard CMOS technology.
Abstract: Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. Channel coding can be used to lower the required signal-to-noise ratio for a specific bit error rate in a channel. There are numerous codes that can be used to approach the theoretical Shannon limit, which is the maximum information transfer rate of a communication channel for a particular noise level. However, the complexity of these codes prohibits their use in high-speed inter-chip applications. A low-complexity signaling scheme is proposed here. This method can achieve 3-5-dB coding gain over uncoded four-level pulse amplitude modulation (PAM). The receiver for this signaling scheme along with a regular 4-PAM receiver was designed and implemented in a 0.18-mum standard CMOS technology. Experimental results show that the receiver is functional up to 2.5 Gb/s. This was verified with a bit error rate tester (BERT) and we were able to achieve error free operation at 2.5-Gb/s channel transfer rate. The entire receiver for this scheme consumes 22 mW at 2.5 Gb/s and occupies an area of 0.2 mm 2.
3 citations