There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

A low-power low-noise CMOS amplifier for neural recording applications

The authors discuss high-voltage power conversion. Conventional series connection and three-level voltage source inverter techniques are reviewed and compared. A novel versatile multilevel commutation cell is introduced: it is shown that this topology is safer and more simple to control, and delivers purer output waveforms. The authors show how this technique can be applied to either choppers or voltage-source inverters and generalized to any number of switches.<<ETX>>

Multi-level conversion : high voltage choppers and voltage-source inverters

/pdf/statistical-theory-of-communication-4wy4yg9ato.pdf

Statistical Theory of Communication

Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

An overview of sigma-delta converters

Introduction. UWB Channel Models. Modulation Schemes. Receiver Structures. Integrated Circuit Topologies. UWB Antennas. Medium Access Control. Positioning.

UWB theory and applications

High-speed high-resolution analog-to-digital converters (ADC) are one of the major bottlenecks in digital communication systems. This work investigates the ADCs bit requirements for wired communication applications and presents an efficient partial analog equalization approach to improve the performance of the front-end ADC by 2-3 bits. The proposed partial analog equalizer along with a 6-bit 400-MHz flash ADC consumes 106 mW of power with 34-dB SNDR in a 0.18-/spl mu/m CMOS process. For a 400-Mb/s data transmission over a 240-m coaxial channel, experimental results show an error performance improvement equivalent to an 8-bit ADC system.

A 400-MHz 6-bit ADC with a partial analog equalizer for coaxial cable channels

A high-speed analog Viterbi detector based on 4-PAM duobinary scheme is designed and implemented in a 0.25 µm CMOS process. This chip is the first analog integrated implementation of a reduced state sequence detector. Due to test equipment limitations, experimental results are given for 200 Mb/s operation while simulation results indicate a speed of 1 Gb/s. Power dissipation is 60 mW from a 2.5V supply.

High-speed CMOS analog Viterbi detector for 4-PAM partial response signalling

This brief presents an open-loop readout circuit for capacitive accelerometers. It combines a ratiometric approach with charge balancing for high linearity. The charge balance is implemented with a delta–sigma loop that acts as an analog-to-digital converter for a readout signal. The system avoids the low-signal-tone power levels present in current charge-balanced implementations, making it a flexible readout technique for accelerometers with varying sensitivities and dynamic ranges.

https://www.eecg.toronto.edu/~johns/nobots/papers/pdf/2015_amini.pdf

A Flexible Charge-Balanced Ratiometric Open-Loop Readout System for Capacitive Inertial Sensors

A low power switched-capacitor (SC) integrator based on a capacitive charge-pump (CP) is proposed. The CP integrator circuit consumes approximately a quarter of the power of a conventional SC integrator while maintaining the same thermal noise performance. Power consumption of the CP integrator is analysed and compared with a conventional parasitic-insensitive integrator. Simulation results verifying the thermal noise and settling performance of the CP integrator are also provided.

https://www.eecg.toronto.edu/~johns/nobots/papers/pdf/2010_nilchi.pdf

Charge-pump based switched-capacitor integrator for ΔΣ modulators

A strategy for tuning continuous-time filters is presented. Instead of relying on matched integrated elements, this technique uses an adaptive algorithm to tune both the poles and zeros of the filter. Circuit details and experimental results are given. The tunable filter was fabricated with a 3- mu m CMOS process. The tuning circuit was implemented with an on-chip gradient filter and off-chip discrete components. Simulation and experimental results show the validity of the proposed tuning approach. >

David A. Johns

Papers

A 400-MHz 6-bit ADC with a partial analog equalizer for coaxial cable channels

High-speed CMOS analog Viterbi detector for 4-PAM partial response signalling

A Flexible Charge-Balanced Ratiometric Open-Loop Readout System for Capacitive Inertial Sensors

Charge-pump based switched-capacitor integrator for ΔΣ modulators

An adaptive tuning circuit for integrated continuous-time filters