There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

A low-power low-noise CMOS amplifier for neural recording applications

The authors discuss high-voltage power conversion. Conventional series connection and three-level voltage source inverter techniques are reviewed and compared. A novel versatile multilevel commutation cell is introduced: it is shown that this topology is safer and more simple to control, and delivers purer output waveforms. The authors show how this technique can be applied to either choppers or voltage-source inverters and generalized to any number of switches.<<ETX>>

Multi-level conversion : high voltage choppers and voltage-source inverters

/pdf/statistical-theory-of-communication-4wy4yg9ato.pdf

Statistical Theory of Communication

Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

An overview of sigma-delta converters

Introduction. UWB Channel Models. Modulation Schemes. Receiver Structures. Integrated Circuit Topologies. UWB Antennas. Medium Access Control. Positioning.

UWB theory and applications

A third-order passive switched-capacitor low-pass filter is presented together with experimental results. The current input-voltage output filter structure realizes complex-conjugate poles although it is composed of switches and capacitors. The results are verified with measurements performed on the filter prototype integrated in a 0.13- $\mu \text{m}$ CMOS technology. The prototype has a cut-off frequency of 470 kHz, 150- $\mu \text{W}$ power consumption from 1.2-V power supply, 92-dB SFDR, and an active area of 0.06 mm2. The switch-capacitor filter was obtained using a continuous-time model that is also described here and is useful for design, analysis, and simulation of oversampled switched-capacitor circuits. The model is applicable to a variety of topologies including multi-phase passive switched-capacitor filters, switched-capacitor integrators, as well as switched-capacitor dc/dc converters.

A Third-Order Integrated Passive Switched-Capacitor Filter Obtained With a Continuous-Time Design Approach

In low voltage signaling for chip-to-chip digital communication, noise is a crucial factor and since common-mode noise is prevalent on matched printed circuit board (PCB) traces, differential signaling is an effective method for chip-to-chip communication. However, it needs two signal paths for transmitting one bit. Multi-level signaling can be used to reduce the number of required signal paths for transmitting one bit. To reduce the required signal power, this paper investigates several coding schemes for this application. A novel scheme, which improves the performance of ordinary 4-level pulse amplitude modulation (PAM) by roughly 3 dB, is proposed. Finally a low complexity method for an analog implementation of this scheme is presented.

https://ieeexplore.ieee.org/iel5/7897/21785/01011049.pdf

Power efficient chip-to-chip signaling schemes

This paper introduces a power management IC (PMIC) targeted for wide range of dc-dc converter applications where low volume implementation is the priority, such as battery powered portable applications. The low volume implementation is achieved by a combined switched-capacitor and inductor based architecture, allowing drastic reduction of output filter volumes without increasing switching losses of the system. The introduced solution is highly configurable to support different voltages and current levels, depending on specific application requirements, and hence can be utilized in a wide range of applications including multi-level and differential power converters. The integrated solution also features mixed signal current program mode compatibility, allowing inherent protection, dynamic efficiency optimization and simpler control with superior dynamic response. The custom PMIC is fabricated in a standard 0.13µ CMOS process and results are obtained through operation at 9.3 MHz switching frequency, allowing for the use of small filter components.

A configurable power management IC for low-volume dc-dc converter applications with high frequency current programmed mode control

The least mean square (LMS) algorithm has practical problems in the analog domain mainly due to DC offset effects. If digital LMS adaptation is used, a digitizer (analog-to-digital converter or comparator) is required for each gradient signal as well as the filter output. Furthermore, in some cases the state signals are not available anywhere in the analog signal path necessitating additional analog filters. Here, techniques for digitally estimating the gradient signals required for the LMS adaptation of analog filters are described. The techniques are free from DC offset effects and do not require access to the filter's internal state signals. Digitizers are required only on the input and error signal. The convergence rate and misadjustment are identical to traditional LMS adaptation, but an additional matrix multiplication is required for each iteration. Hence, analog circuit complexity is reduced but digital circuit complexity is increased with no change in overall performance making it an attractive option for mixed-signal integrated systems in digital CMOS. Signed and subsampled variations of the adaptive algorithm can provide a further reduction in analog and digital circuit complexity, but with a slower convergence rate. Theoretical analyses, behavioral simulations, and experimental results from an integrated filter are all presented.

/pdf/digital-lms-adaptation-of-analog-filters-without-gradient-2qjy7et1kw.pdf

Digital LMS adaptation of analog filters without gradient information

This paper presents a class-AB sub-GHz RF receiver front-end suitable for ultra-low power application. By exploiting transistors' class-AB operation in both the RF and baseband sections, the receiver front-end achieves a very low sensitivity and an elevated blocker tolerance while keeping a low power consumption. Such performance makes the receiver suitable for both short-range (e.g. 802.15.4) and long-range (e.g. LoRa) applications. The proposed RF front-end has been implemented in 0.13um CMOS technology, operates in the 868/915MHz ISM bands, and exhibits an in-band gain of 50dB, noise figure of 2.7dB, out-of-band HP3 of +2dBm, out-of-band IIP2 of +37dBm, out-of-band P1dB of −10.5dBm, while draining 2.1mA from a 1.2 V supply.

/pdf/a-low-power-sub-ghz-rf-receiver-front-end-with-enhanced-38awa86dc6.pdf

David A. Johns

Papers

A Third-Order Integrated Passive Switched-Capacitor Filter Obtained With a Continuous-Time Design Approach

Power efficient chip-to-chip signaling schemes

A configurable power management IC for low-volume dc-dc converter applications with high frequency current programmed mode control

Digital LMS adaptation of analog filters without gradient information

A low-power sub-GHz RF receiver front-end with enhanced blocker tolerance