There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

A low-power low-noise CMOS amplifier for neural recording applications

The authors discuss high-voltage power conversion. Conventional series connection and three-level voltage source inverter techniques are reviewed and compared. A novel versatile multilevel commutation cell is introduced: it is shown that this topology is safer and more simple to control, and delivers purer output waveforms. The authors show how this technique can be applied to either choppers or voltage-source inverters and generalized to any number of switches.<<ETX>>

Multi-level conversion : high voltage choppers and voltage-source inverters

/pdf/statistical-theory-of-communication-4wy4yg9ato.pdf

Statistical Theory of Communication

Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

An overview of sigma-delta converters

Introduction. UWB Channel Models. Modulation Schemes. Receiver Structures. Integrated Circuit Topologies. UWB Antennas. Medium Access Control. Positioning.

UWB theory and applications

Analog Viterbi decoders have recently been shown to be viable alternatives to their digital counterparts. In fact, a commercial analog class-IV partial-response sequence detector for magnetic read channels has already been reported. Analog decoders offer the advantages of reduced power and size primarily due to the elimination of the A/D. The analog Viterbi decoder described here is less complex and more robust compared to other reported realizations. The decoder is based on a new derivation of the difference-metric algorithm which is developed from an analog implementation perspective. This has resulted in a decrease in hardware complexity thereby making an analog approach more attractive for today's demanding high-speed, low-power, and small-size applications, such as magnetic disk-drive storage systems. The decoder was fabricated in a 0.8-/spl mu/m BiCMOS process. It consists of two time-interleaved dicodes and the interleaving circuitry. The decoder was tested at up to 100 MS/s. However, since each dicode was also tested at this speed, the class-IV decoder should be capable of operating at 200 MS/s. Direct experiments at this speed were not possible due to the test equipment limitations. The chip consumes 30 mW from a 3.3-V power supply and occupies a core area of 0.5 mm/sup 2/.

/pdf/an-integrated-200-mhz-3-3-v-bicmos-class-iv-partial-response-1bo0ce0t9g.pdf

An integrated 200-MHz 3.3-V BiCMOS class-IV partial-response analog Viterbi decoder

To aid in the search for better adaptive filter structures, a method is presented to obtain the gradients required to adapt general state-space filters. Unfortunately, the number of computations for this general case is quite high. To reduce the number of computations, two new state-space adaptive filters are introduced. One application where these new structures are shown to be useful is in oversampled filtering where an estimate of the final pole locations is known and the adaptive filter is required only to fine-tune the transfer function. It is shown that for this type of application, the new adaptive structures can have much improved adaptation rates and roundoff noise performance as compared to the corresponding direct-form realizations. >

Adaptive recursive state-space filters using a gradient-based algorithm

Recently, a new architecture was proposed which utilizes the concept of time-interleaving in oversampling converters. Using this architecture, one is theoretically able to achieve higher resolutions by using an array of interconnected modulators without increasing the oversampling ratio or order of the modulators. Alternatively, the same resolution can be maintained with wider bandwidth input signals. This paper presents the first experimental results on this new family of modulators. As well, the practical issue of component mismatch for these converters are studied and some suggestions are made to alleviate the effects of this problem. >

Mismatch effects in time-interleaved oversampling converters

A 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth is implemented in 0.18 mum CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0-3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).

/pdf/a-12-bit-3-125-mhz-bandwidth-0-3-mash-delta-sigma-modulator-4mckp1wtmj.pdf

A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator

In this paper the use of incremental A/D converters with low oversampling ratios is investigated. Incremental A/D converters are able to achieve a higher SQNR than delta-sigma modulators at oversampling ratios below 4, allowing them to operate as higher bandwidth converters with medium resolution. The impact of removing the input S/H, as well as analyzing their behaviour at an OSR as low as 1 is explored. An eighth-order cascaded incremental A/D converter is analyzed and shown as an example.

/pdf/incremental-data-converters-at-low-oversampling-ratios-18psdxod60.pdf

David A. Johns

Papers

An integrated 200-MHz 3.3-V BiCMOS class-IV partial-response analog Viterbi decoder

Adaptive recursive state-space filters using a gradient-based algorithm

Mismatch effects in time-interleaved oversampling converters

A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator

Incremental Data Converters at Low Oversampling Ratios