There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

A low-power low-noise CMOS amplifier for neural recording applications

The authors discuss high-voltage power conversion. Conventional series connection and three-level voltage source inverter techniques are reviewed and compared. A novel versatile multilevel commutation cell is introduced: it is shown that this topology is safer and more simple to control, and delivers purer output waveforms. The authors show how this technique can be applied to either choppers or voltage-source inverters and generalized to any number of switches.<<ETX>>

Multi-level conversion : high voltage choppers and voltage-source inverters

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Statistical Theory of Communication

Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

An overview of sigma-delta converters

Introduction. UWB Channel Models. Modulation Schemes. Receiver Structures. Integrated Circuit Topologies. UWB Antennas. Medium Access Control. Positioning.

UWB theory and applications

A 10b pipelined ADC has been realized in a digital 90 nm CMOS technology using techniques such as switched opamps and switched-input buffers. Measurements show that this ADC samples at 12 MS/s achieving a peak SNDR of 52.6 dB using a 1.2 V supply. It consumes 3.3 mW and occupies 0.3 mm/sup 2/ core area.

A 3.3 mW 12 MS/s 10b pipelined ADC in 90 nm digital CMOS

A 15-bit low-power incremental ADC is designed for sensor applications The ADC is designed to be frequency-scalable by 1000 times from 167S/s to 167kS/s To reduce power, an opamp with class AB characteristics is used The design was fabricated in 018/Ltm CMOS and occupies an area of 035mm2 Configured to operate at full-rate as a Delta-Sigma modulator, the ADC achieves 918dB peak SNDR while consuming 83µW from a 18-V supply Operating as an incremental converter, the ADC powers off periodically to achieve frequency scalability, maintaining 847dB to 889dB peak SNDR while operating from 167S/S to 167kS/s and scaling analog power by up to 500 times

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A frequency-scalable 15-bit incremental ADC for low power sensor applications

A transimpedance amplifier with differential DC-coupled photocurrent sensing was integrated in a standard 0.35 /spl mu/m CMOS process. It achieves 33 k/spl Omega/ transimpedance gain and a bandwidth of 255 MHz with a 2 pF photodiode capacitance. This design exhibits 40 dB power supply rejection ratio and an average input noise of (6.8pA)/(/spl radic/Hz). Power dissipation is 30 mW from a 3 V supply.

A transimpedance amplifier with DC-coupled differential photodiode current sensing for wireless optical communications

With the growing demand for high-speed transmission of digital data, there is a challenge for utilizing the existing copper plant as the transmission medium, especially for short-hop links. This medium offers a lower cost to a fiber medium, but requires more sophisticated electronics to account for electromagnetic emissions, cross-talk, and cable loss. These include pulse shaping filters, cross-talk cancelers, and equalizers. To maintain system cost at a minimum, analog solutions are preferred. A continuous-time tunable biquad implemented in a 0.8 /spl mu/m BiCMOS process and configured as an adaptive pulse-shaping filter is described. The biquad is tunable over the range 10-230 MHz with variable Q factors. It is composed of five transconductance-C integrators each dissipating a static power of 10 mW at 5 V. A method for adapting the filter's pole-frequency and Q-factor while servicing 100 Mb/s NRZ data is presented together with experimental results.

A 100 Mb/s BiCMOS adaptive pulse-shaping filter

In this paper a low-power switched-capacitor integrator based on a capacitive charge-pump (CP) is presented, and its practical effects are discussed. The CP integrator is employed as the first stage of a ΔΣ ADC. The 0.13 μm CMOS prototype of the CP based ADC achieves the same performance as a conventional ADC while consuming 66% lower OTA power in the front-end integrator. The CP based modulator realizes 87.8 dB SNDR, 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth with 148 W power consumption. The conventional ADC has similar performance but dissipates 241 W. The energy required per conversion-step for the CP based ADC (0.369 pJ/step) is almost 40% lower than that of the conventional ADC (0.607 pJ/step).

/pdf/a-low-power-delta-sigma-modulator-using-a-charge-pump-4fynlqetuk.pdf

David A. Johns

Papers

A 3.3 mW 12 MS/s 10b pipelined ADC in 90 nm digital CMOS

A frequency-scalable 15-bit incremental ADC for low power sensor applications

A transimpedance amplifier with DC-coupled differential photodiode current sensing for wireless optical communications

A 100 Mb/s BiCMOS adaptive pulse-shaping filter

A Low-Power Delta-Sigma Modulator Using a Charge-Pump Integrator