This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

Contact Structure of Semiconductor Device

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Process Technology Variation

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μΑ/μm (856μΑ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V V min for 8T logic libraries, as well as 0.62V and 0.52V V min for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm I off , and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high f T /f MAx of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high f MAx extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.

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22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications

We investigate the effectiveness of source/drain (S/D) underlap regions in limiting the source to drain tunneling (SDT) current in Si and Ge 096 Sn 004 nanowire MOSFETs (NWFETs), using rigorous ballistic quantum transport simulations Our simulation results indicate that with a carefully chosen length of S/D underlap regions, GeSn p-NWFETs can outperform Si p-NWFETs, despite having a higher component of SDT current in OFF-state

Impact of Source/Drain Underlap on the Ballistic Performance of Silicon and Germanium-Tin Nanowire p-MOSFETs

Aluminium nitride thin films directly grown on conducting boron-doped nanocrystalline diamond films without using buffer layer for high frequency applications

Significant self-heating affects both the performance and reliability of devices. The estimation of maximum temperature (Tmax) and the location of hot-spot in the device is important from the reliability point of view. But it is to be noted that the thermal sub-circuit in any compact model of the device needs to find an equivalent temperature denoted as Teqt in the device instead of Tmax to model the temperature dependence of device electrical parameters. In this paper, we demonstrate the importance of Teqt in compact modeling of devices using well-calibrated TCAD simulation. We compute the thermal resistance from Teqt data for a device which is termed as equivalent thermal resistance (Rth,eqt) and demonstrate its bias independence. Furthermore, we propose the use of Rth,eqt in self-heating compact model for GaN-HEMT by incorporating the Rth,eqt based thermal sub-circuit in an existing drain current compact model. An excellent match was seen between the Rth,eqt based compact model and the measurements whereas maximum temperature based model gives higher device temperature and hence larger drop in current at higher voltages.

Significance of Equivalent Channel Temperature in Compact Modeling of GaN HEMTs

In this work, diamond thin films were deposited using hot filament chemical vapour deposition (HFCVD) technique on Si substrate. Diamond films are typically classified into nano-crystalline diamond (NCD; grain size 500 nm) based on their grain size. Process parameters such as the ratio of methane and hydrogen concentration (%CH4/H2) and chamber pressure were varied to grow MCD and NCD films. NCD and MCD films will be used as substrate to improve the performance of MEMS resonator. Structural characteristics and quality of the MCD and NCD films were confirmed using Raman spectroscopy and the surface features were imaged using high resolution scanning electron microscopy (HRSEM).

Growth Mechanism and Structural Characterization of Nano-crystalline Diamond (NCD) and Micro-crystalline Diamond (MCD) Films Deposited on Silicon Substrates

Thermal behavior in multi-layered semiconductor structures like the one present in a Gallium Nitride high electron mobility transistor (GaN-HEMT) is investigated for the heat-flow towards the substrate A compact analytical model is formulated to predict the peak as well as depth dependent temperature in the structure Modeling results are verified against detailed three-dimensional TCAD thermal simulations of GaN-on-Si structures with GaN layer thickness of $\mathbf{3}\mu\mathbf{m}$ and Si substrate thickness of $\mathbf{100}\mu\mathbf{m}$  Excellent modeling accuracy is observed for different heat source geometries and power dissipation In addition, the proposed model is extended to estimate the static thermal coupling factor in multifinger transistors with high level of accuracy

Deleep R. Nair

Papers

Impact of Source/Drain Underlap on the Ballistic Performance of Silicon and Germanium-Tin Nanowire p-MOSFETs

Aluminium nitride thin films directly grown on conducting boron-doped nanocrystalline diamond films without using buffer layer for high frequency applications

Significance of Equivalent Channel Temperature in Compact Modeling of GaN HEMTs

Growth Mechanism and Structural Characterization of Nano-crystalline Diamond (NCD) and Micro-crystalline Diamond (MCD) Films Deposited on Silicon Substrates

Modeling Thermal Behavior in Multi-layered GaN HEMT-like Structures