D
Deleep R. Nair
Researcher at Indian Institute of Technology Madras
Publications - 74
Citations - 721
Deleep R. Nair is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Metal gate & Leakage (electronics). The author has an hindex of 12, co-authored 62 publications receiving 632 citations. Previous affiliations of Deleep R. Nair include Indian Institutes of Technology & Indian Institute of Technology Bombay.
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Proceedings ArticleDOI
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process
X. Chen,S. Samavedam,Vijay Narayanan,Kenneth J. Stein,C. Hobbs,Christopher V. Baiocco,Weipeng Li,Jaeger Daniel,M. Zaleski,Haining Yang,Nam-Sung Kim,Yi-Wei Lee,Da Zhang,Laegu Kang,J. Chen,Haoren Zhuang,Arifuzzaman (Arif) Sheikh,J. Wallner,Michael V. Aquilino,Jin-Ping Han,Zhenrong Jin,James Chingwei Li,G. Massey,S. Kalpat,Rashmi Jha,Naim Moumen,R. Mo,S. Kirshnan,X. Wang,Michael P. Chudzik,M. Chowdhury,Deleep R. Nair,C. Reddy,Young Way Teh,Chandrasekharan Kothandaraman,Douglas D. Coolbaugh,Shesh Mani Pandey,D. Tekleab,Aaron Thean,Melanie J. Sherony,Craig S. Lage,J. Sudijono,R. Lindsay,JiYeon Ku,Mukesh Khare,An L. Steegen +45 more
TL;DR: In this article, a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2 was demonstrated.
Proceedings ArticleDOI
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
Siddarth A. Krishnan,Unoh Kwon,Naim Moumen,Matthew W. Stoker,Eric C. Harley,Stephen W. Bedell,Deleep R. Nair,B. Greene,William K. Henson,Murshed M. Chowdhury,D.P. Prakash,Ernest Y. Wu,Dimitris P. Ioannou,Eduard A. Cartier,Myung-Hee Na,S. Inumiya,Kevin McStay,Lisa F. Edge,Ryosuke Iijima,Jin Cai,Martin M. Frank,M. Hargrove,Dechao Guo,Andreas Kerber,Hemanth Jagannathan,Takashi Ando,Joseph F. Shepard,Shahab Siddiqui,Min Dai,Huiming Bu,J. Schaeffer,Jaeger Daniel,Kathy Barla,Thomas A. Wallner,S. Uchimura,Y. Lee,Gauri Karve,Sufi Zafar,Dominic J. Schepis,Yun-Yu Wang,Ricardo A. Donaton,S. Saroop,P. Montanini,Yue Liang,James H. Stathis,Richard Carter,Rohit Pal,Vamsi Paruchuri,H. Yamasaki,J-H Lee,Martin Ostermayr,J.-P. Han,Yue Hu,Michael A. Gribelyuk,Dae-Gyu Park,X. Chen,Srikanth Samavedam,Shreesh Narasimha,Paul D. Agnello,Mukesh Khare,R. Divakaruni,Vijay Narayanan,Michael P. Chudzik +62 more
TL;DR: In this article, the authors leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) high-к/metal gate (HKMG) logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.
Proceedings ArticleDOI
32nm general purpose bulk CMOS technology for high performance applications at low voltage
Franck Arnaud,Jinping Liu,Y.M. Lee,K.Y. Lim,S. Kohler,J. Chen,B.K. Moon,C.W. Lai,M. Lipinski,L. Sang,Fernando Guarin,C. Hobbs,Paulo Ferreira,Kazuya Ohuchi,J. Li,H. Zhuang,P. Mora,Qintao Zhang,Deleep R. Nair,D.H. Lee,K.K. Chan,S. Satadru,S. Yang,J. Koshy,W. Hayter,M. Zaleski,D.V. Coolbaugh,H.W. Kim,Y.C. Ee,J. Sudijono,Aaron Thean,M. Sherony,S. Samavedam,M. Khare,C. Goldberg,A. Steegen +35 more
TL;DR: In this paper, a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack is presented for the first time, and a Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay.
Proceedings ArticleDOI
Scaling of 32nm low power SRAM with high-K metal gate
H.S. Yang,Robert C. Wong,R. Hasumi,Y. Gao,Nam-Sung Kim,Deok-Hyung Lee,Sayeed A. Badrudduza,Deleep R. Nair,Martin Ostermayr,Ho-Kyu Kang,Haoren Zhuang,James Chingwei Li,Laegu Kang,X. Chen,Aaron Thean,Franck Arnaud,L. Zhuang,C. Schiller,D.P. Sun,Y.W. Teh,J. Wallner,Y. Takasu,Kenneth J. Stein,S. Samavedam,Jaeger Daniel,Christopher V. Baiocco,Melanie J. Sherony,Mukesh Khare,Craig S. Lage,J. Pape,J. Sudijono,An L. Steegen,S. Stiffler +32 more
TL;DR: In this article, the authors describe SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2.
Proceedings ArticleDOI
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
Franck Arnaud,Aaron Thean,Manfred Eller,M. Lipinski,Young Way Teh,Martin Ostermayr,K. Kang,Nam-Sung Kim,Kazuya Ohuchi,J.-P. Han,Deleep R. Nair,Jenny Lian,S. Uchimura,S. Kohler,S. Miyaki,Paulo Ferreira,J-H. Park,Masafumi Hamaguchi,Katsura Miyashita,R. Augur,Qintao Zhang,K. Strahrenberg,S. ElGhouli,J. Bonnouvrier,Fumiyoshi Matsuoka,Richard Lindsay,J. Sudijono,Frank Scott Johnson,JiYeon Ku,M. Sekine,An L. Steegen,Ron Sampson +31 more
TL;DR: In this article, the authors present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal gate-first architecture.