International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

This article presents the design of a highly linear high-power silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) 802.11ac/ax wireless local area network (WLAN) power amplifiers (PAs). The challenges associated with electrothermal effects on the dynamic operation of WLAN PAs are first discussed. We then propose the design methods that take into account the electrothermal transient effect to improve linear output power ( $P_{\mathrm {OUT}}$ ) and dynamic error vector magnitude (DEVM). A compact four-way output transformer balun is proposed to achieve efficient power combining, and a built-in 2nd-harmonic short is demonstrated by using a novel multi-layered metallization scheme. A thermally compensating dynamic bias circuit that improves the DEVM and reduces memory effects is designed with an integrated temperature sensor. Different SiGe HBT array layouts, laterally and vertically arranged, of the output stage of the PA are also investigated. With the 802.11ac MCS9 VHT80 test signals, the DEVM of a PA with a laterally arranged output stage is lower than that of its vertical counterpart. This suggests the importance of the layout on the transistor electrothermal transient effect. The PA with the laterally arranged output stage shows a $P_{\mathrm {OUT}}$ of 22.5/23.6/23.2 dBm (DEVM = −35 dB) with 10.0/12.2/11.2% power-added efficiency (PAE) at 5210/5530/5855 MHz under an 802.11ac MCS9 VHT80 test signal at 50% duty cycle. Good DEVM performance was measured under the test signal with various duty cycles, indicating that the proposed PA is thermally robust. The design supports the 802.11ax MCS11 VHT80 signals with 19.4-dBm $P_{\mathrm {OUT}}$ , satisfying a DEVM of −40 dB.

Highly Linear High-Power 802.11ac/ax WLAN SiGe HBT Power Amplifiers With a Compact 2nd-Harmonic-Shorted Four-Way Transformer and a Thermally Compensating Dynamic Bias Circuit

An accurate analytic model is proposed for estimating the junction temperature and thermal resistance in silicon–germanium heterojunction bipolar transistors (SiGe HBTs) including the back-end-of-line (BEOL) metal layers. The model uses an average value of thermal conductivity in order to include the temperature dependence of thermal resistance. The parameters corresponding to the thermal conductivity and the BEOL thermal resistance used in the model are extracted following a recently reported methodology. The proposed model is scalable in nature and verification with experimental data shows an excellent accuracy across different emitter geometries of SiGe HBTs fabricated in STMicroelectronics B9MW technology. Compact model simulations show that the proposed model simulates around 23% faster compared with an existing state-of-the-art iterative method.

Accurate Modeling of Thermal Resistance for On-Wafer SiGe HBTs Using Average Thermal Conductivity

In this letter, we present a detailed investigation on how dynamic thermal phenomena take place in state-of-the-art SiGe HBTs when excited by sinusoidal power dissipation. To give a better insight into the mechanisms leading to the thermal impedance ( $\text{Z}_{{\textsf {th}}})$ decay, we introduce the concept of thermal penetration depth; then, with the help of 3-D thermal simulations, we illustrate its effect on the spatial distribution of the temperature variations within the transistor structure, according to the frequency of operation. In order to experimentally analyze the impact on a real device, dedicated HBT structures are designed; they consist of multi-finger SiGe HBTs realized in B55 technology from STMicroelectronics, for which modifications are made in the back-end-of-line (BEOL) metallization or in the transistor layout, increasing its deep trench isolation enclosed area. For these transistors, $\text{Z}_{{\textsf {th}}}$ measurements are carried out in the frequency range 10kHz–1GHz; the results show that the metal connections configuration in the BEOL or layout modifications can considerably impact the $\text{Z}_{{\textsf {th}}}$ decay at low frequencies. An identical $\text{Z}_{{\textsf {th}}}$ trend is instead measured above 1–2 MHz, demonstrating that at higher frequencies just the region close to the heat source is concerned by dynamic thermal phenomena.

https://hal.archives-ouvertes.fr/hal-01639596/document

Thermal Penetration Depth Analysis and Impact of the BEOL Metals on the Thermal Impedance of SiGe HBTs

In this paper, an electrothermal-based junction temperature estimation model is proposed for an asymmetric half-bridge converter of a switched reluctance motor drive system. In the current chopping control mode, there exists a particularly uneven temperature distribution on converters due to not only the thermal coupling effects and dissipating boundary conditions, but also the different device losses in the same phase bridge. For the purpose of precise estimation for junction temperature, first, the power loss of converter is accurately calculated by the interpolation method with the help of Simulink and LTspice. Second, the thermal coupling effects and dissipating boundary conditions are analyzed in the three-dimensional finite-element method (FEM) model. According to the step power response extraction, a coupling impedance matrix is used to describe the nonnegligible thermal coupling effects between devices, and the complete heatsink can be decoupled into multiple subdivisions that represent the different heat dissipating boundary conditions. Then, with coupling impedances and subheatsink impedances in series, a compact RC network model can be built for junction temperature estimation. Consequently, analytical investigation in conjunction with FEM simulation and experiment measurements demonstrate the validity of the proposed model.

Electrothermal-Based Junction Temperature Estimation Model for Converter of Switched Reluctance Motor Drive System

In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.

Analytic Estimation of Thermal Resistance in HBTs

In this paper we study and analyze the existing techniques in literature to extract the self-heating thermal resistance from the measured DC electrical behaviour of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) focusing their dependence on device junction temperature and propose a simple extraction technique that shows superior accuracy than the existing extraction methodologies. Our approach is scalable and validated with model card simulations across different emitter geometries for a wide temperature range. We also present the applicability of our approach on measured data of a SiGe HBT fabricated in STMicroelectronics B55 process.

Extracting the temperature dependence of thermal resistance from temperature-controlled DC measurements of sige HBTs

In this brief, we propose a simple approach to extract the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs). A finite value of BEOL thermal resistance obtained following our approach confirms a non-negligible heat flow toward BEOL. The proposed extraction technique is validated with iterative solutions and measured data of silicon–germanium HBTs fabricated in the STMicroelectronics B9MW technology.

Suresh Balanethiram

Papers

Analytic Estimation of Thermal Resistance in HBTs

Accurate Modeling of Thermal Resistance for On-Wafer SiGe HBTs Using Average Thermal Conductivity

Extracting the temperature dependence of thermal resistance from temperature-controlled DC measurements of sige HBTs

Thermal Penetration Depth Analysis and Impact of the BEOL Metals on the Thermal Impedance of SiGe HBTs

Extraction of BEOL Contributions for Thermal Resistance in SiGe HBTs