This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

Contact Structure of Semiconductor Device

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Process Technology Variation

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μΑ/μm (856μΑ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V V min for 8T logic libraries, as well as 0.62V and 0.52V V min for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm I off , and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high f T /f MAx of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high f MAx extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.

/pdf/22nm-fdsoi-technology-for-emerging-mobile-internet-of-things-4yne7lth59.pdf

22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications

Surface roughness is an important factor that influences the reliability and performance of radio frequency microelectromechanical systems switches. The presence of surface roughness impedes a perfect contact in the down-state condition of the switch which in turn affects the following parameters—resonant frequency, down-state capacitance, and isolation at resonance. The result is a significant deviation from the electromagnetic characteristics simulated by assuming flat surfaces making a perfect contact. However, creating a rough topography manually is cumbersome. A Visual Basic Script code for generating rough surfaces of any average value and standard deviation has been developed. The code runs on High Frequency Structure Simulator platform. This paper focuses on the simulations that include the effect of surface roughness on both the beam and the dielectric layer using a 3-D geometric model by representing surface asperities as an array of pyramids, the heights of which follow a Gaussian distribution. This assumption takes into account of the statistical nature of surface roughness. The results of simulation indicate that the presence of surface roughness reduces down-state capacitance and isolation and shifts the resonant frequency from the X-band (8–12 GHz) for which it was originally designed.

Study of the Effect of Surface Roughness on the Performance of RF MEMS Capacitive Switches Through 3-D Geometric Modeling

Silicon-germanium is an alternative channel material for pMOS FETs at 32-nm node and beyond because of lower threshold voltage and higher channel mobility in high-k metal gate technology. However, gate-induced drain leakage (GIDL) is a major concern at low power technology nodes because of band-to-band and trap-assisted tunneling (TAT) due to reduced bandgap. Here, we have studied the GIDL dependence on temperature as well as drain and substrate bias. Experimental results and Technology computer-aided design (TCAD) simulations suggest that the mechanism responsible for GIDL during off state is mostly phonon-assisted band-to-band tunneling (BTBT) in the top SiGe layer near the drain surface and is further contributed by BTBT at the drain sidewall junction. Other GIDL mechanisms such as TAT at the extension/sidewall dominate for other drain, gate, and substrate bias voltages.

Analysis of Gate-Induced Drain Leakage Mechanisms in Silicon-Germanium Channel pFET

This letter presents a technique to accurately predict the proximity effect losses in spiral inductors with variable width and spacing (taper) across the turns. The change in magnetic flux in a spiral turn due to the nearby non-uniformly spaced traces is considered while developing expression that captures proximity effect. A broadband, scalable, and frequency-independent compact model is developed for tapered inductors using the proposed technique. Resistance, inductance, and quality factor ( ${Q}$ ) plots are shown for spiral inductors with different values of taper. Excellent agreement between model and EM simulated/measured data demonstrates the scalability of the proposed model. The proposed model can be used to accurately predict the high ${Q}$ possible with tapered inductors.

Compact Modeling of Proximity Effect in High- ${Q}$ Tapered Spiral Inductors

RF MEMS capacitive shunt switches with a dielectric-on-metal (DOM) capacitor, which are widely used for microwave applications in communication field, suffer from some serious drawbacks. A significant shift is observed in the resonant frequency of these switches due to the reduction in the down-state capacitance caused by the surface roughness of the dielectric layer. In order to achieve accurate down-state capacitance, a thin layer of floating metal is deposited on the dielectric layer converting the DOM switch to an MIM switch. The MIM switch opens up interesting possibilities in the design, such as achieving flexibility in the operating frequency of the switch. This paper reports a novel method to achieve design flexibility for multi-frequency operation in switches, by effectively utilizing the equipotential nature of the floating metal in the MIM capacitor. Unlike in a DOM switch, the resonant frequency can be varied by changing merely the length of the floating metal, without having to make any other structural modifications. This enables to have switches operating at different frequency on the same wafer. The beams of the switches are also designed in such a way as to provide stress resilience, thereby preventing buckling. This paper presents the design, simulation, fabrication and characterization of a switch that operates in the X-band. The fabricated switches show excellent stress resilience. The characterized switch demonstrates a reduction in the resonant frequency in proportion to an increase in the length of the floating metal, hence validating the design flexibility proposed in this paper.

http://iopscience.iop.org/article/10.1088/1361-6439/aa7d21/pdf

Novel RF MEMS capacitive switches with design flexibility for multi-frequency operation

At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.

Deleep R. Nair

Papers

Study of the Effect of Surface Roughness on the Performance of RF MEMS Capacitive Switches Through 3-D Geometric Modeling

Analysis of Gate-Induced Drain Leakage Mechanisms in Silicon-Germanium Channel pFET

Compact Modeling of Proximity Effect in High- ${Q}$ Tapered Spiral Inductors

Novel RF MEMS capacitive switches with design flexibility for multi-frequency operation

Oxygen scavenging spacer for a gate electrode