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Dennis J. Yost
Researcher at Texas Instruments
Publications - 7
Citations - 427
Dennis J. Yost is an academic researcher from Texas Instruments. The author has contributed to research in topics: Etching (microfabrication) & Dielectric. The author has an hindex of 5, co-authored 7 publications receiving 427 citations. Previous affiliations of Dennis J. Yost include Applied Materials.
Papers
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Patent
Integrated low k dielectrics and etch stops
Claes H. Bjorkman,Yu Melissa Min,Hongquing Shan,David Cheung,Wai-Fan Yau,Kuo-Wei Liu,Nasreen Gazala Chopra,Gerald Zheyao Yin,Farhad Moghadam,Judy H. Huang,Dennis J. Yost,Betty Tang,Yunsang Kim +12 more
TL;DR: In this paper, a method of depositing and etching dielectric layers has been proposed for the formation of horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide.
Patent
Metallization process for a semiconductor device
TL;DR: In this article, the authors proposed a collimation-based contact structure for high aspect ratio contacts in VLSI multilevel interconnected devices such as dynamic random access memories (DRAM).
Patent
Global planarization process using patterned oxide
Dennis J. Yost,Patrick M. Martin +1 more
TL;DR: In this article, the authors proposed a method for planarizing the surface of a layer in a semiconductor device by forming conductor regions 24, 26, and 28 on a layer of the device and forming an insulator layer 40 over the first insulator regions 30, 32, and 34.
Patent
Method of depositing and etching dielectric layers
Claes H. Bjorkman,David Cheung,Nasreen Gazala Chopra,Judy H. Huang,Yunsang Kim,Kuo-Wei Liu,Yu Melissa Min,Farhad Moghadam,Hongqing Shan,Betty Tang,Wai-Fan Yau,Gerald Zheyao Yin,Dennis J. Yost +12 more
TL;DR: In this article, a method of depositing and etching dielectric layers having low Dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects was proposed.
Patent
Global planarization using a polyimide block
Patrick M. Martin,Dennis J. Yost +1 more
TL;DR: A semiconductor device includes conductor regions 24 and 26 on a layer of the semiconductor, a first insulator layer 28 over and between the conductor regions, polyimide regions 30, 32, and 34 over the first layer, and a second layer 38 over the second layer.