An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas comprising carbon at a constant RF power level. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.

Plasma processes for depositing low dielectric constant films

A faceplate for a showerhead of a semiconductor wafer processing system is provided. The faceplate has a plurality of gas passageways to provide a plurality of gases to the process region without commingling those gases before they reach the processing region within a reaction chamber. The showerhead includes a faceplate and a gas distribution manifold assembly. The faceplate defines a plurality of first gas holes that carry a first gas from the manifold assembly through the faceplate to the process region, and a plurality of channels that couple a plurality of second gas holes to a radial plenum that receives the second gas from the manifold assembly. The faceplate and the manifold assembly are each fabricated from a substantially solid nickel material.

Dual gas faceplate for a showerhead in a semiconductor wafer processing system

An interferometric modulator manufactured according to a particular set of processing parameters may have a non-zero offset voltage. A process has been developed for modifying the processing parameters to shift the non-zero offset voltage closer to zero. For example, the process may involve identifying a set of processing parameters for manufacturing an interferometric modulator that results in a non-zero offset voltage for the interferometric modulator. The set of processing parameters may then be modified to shift the non-zero offset voltage closer to zero. For example, modifying the set of processing parameters may involve modifying one or more deposition parameters used to make the interferometric modulator, applying a current (e.g., a counteracting current) to the interferometric modulator, and/or annealing the interferometric modulator. Interferometric modulators made according to the set of modified processing parameters may have improved performance and/or simpler drive schemes.

Process for modifying offset voltage characteristics of an interferometric modulator

A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.

Method of depositing a low k dielectric with organo silane

A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects

Integrated low k dielectrics and etch stops

A method for etching a dielectric in a thermally controlled plasma etch chamber with an expanded processing window The method is adapted to incorporate benefits of a the thermal control and high evacuation capability of the chamber Etchent gases include hydrocarbons, oxygen and inert gas Explanation is provided for enablling the use of hexafluoro-1,3-butadiene in a capacitively coupled etch plasma The method is very useful for creating via, self aligned contacts, dual damascene, and other dielectric etch

Etch method using a dielectric etch chamber with expanded process window

A photoresist plasma pretreatment performed prior to a plasma oxide etch. The plasma pretreatment is performed with an argon plasma or a carbon tetrafluoride and trifluoromethane plasma with lower power than in the main etch or is performed with a plasma of difluoromethane or trifluoromethane and carbon monoxide but no argon diluent gas. Thereby, striations on the oxide wall are reduced.

Plasma pretreatment of photoresist in an oxide etch process

Apparatus for plasma etching a layer of material upon a substrate comprising an anode having a first region protruding from a second region, wherein the second region defines a plane and the first region extends from said plane. In one embodiment, at least one solenoid is disposed near the apparatus to magnetize the plasma.

Apparatus for uniformly etching a dielectric layer

Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises exposing the dielectric material to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas selected from the group consisting of carbon monoxide (CO), argon, and combinations thereof. A volumetric flow ratio of the additive gas to the fluorine-containing etchant gas is within the range of about 1.25:1 to about 20:1 (more typically, about 2.5:1 to about 20:1), depending on the particular fluorine-containing etchant gas used. The method provides good control over critical dimensions and etch profile during trench etching. Also disclosed herein is a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.

Yunsang Kim

Papers

Integrated low k dielectrics and etch stops

Etch method using a dielectric etch chamber with expanded process window

Plasma pretreatment of photoresist in an oxide etch process

Apparatus for uniformly etching a dielectric layer

Method of etching a trench in a silicon-containing dielectric material