D
Dexian Tang
Researcher at Tokyo Institute of Technology
Publications - 8
Citations - 185
Dexian Tang is an academic researcher from Tokyo Institute of Technology. The author has contributed to research in topics: Transceiver & Transmitter. The author has an hindex of 5, co-authored 8 publications receiving 112 citations.
Papers
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Proceedings ArticleDOI
An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS
Hanli Liu,Zheng Sun,Dexian Tang,Hongye Huang,Tohru Kaneko,Wei Deng,Rui Wu,Kenichi Okada,Akira Matsuzawa +8 more
TL;DR: This paper demonstrates a Bluetooth Low-Energy transceiver (TRX) achieving ultra-low-power (ULP) operation for Internet-of-Things (IoT) applications while satisfying all the interference requirements with sufficient margins.
Journal ArticleDOI
A Sub-mW Fractional- ${N}$ ADPLL With FOM of −246 dB for IoT Applications
TL;DR: The proposed ADPLL with scalable power and jitter performance can be utilized for Internet-of-Things (IoT) applications, such as Bluetooth low energy (BLE) and Wi-Fi networks.
Journal ArticleDOI
A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS
Yun Wang,Bangan Liu,Rui Wu,Hanli Liu,Aravind Tharayil Narayanan,Jian Pang,Ning Li,Toru Yoshioka,Yuki Terashima,Haosheng Zhang,Dexian Tang,Makihiko Katsuragi,Dae-Young Lee,Sungtae Choi,Kenichi Okada,Akira Matsuzawa +15 more
TL;DR: The proposed BPOOK wireless transceiver transmits radio frequency signal with amplitude modulated on and off by input baseband data, and meanwhile, the phase is changing between 0° and 180°, achieving doubled spectral efficiency compared with OOK modulation and binary-phase-shift keying (BPSK).
Proceedings ArticleDOI
A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of −246dB for IoT applications in 65nm CMOS
TL;DR: This paper presents a 2.0-to-2.8GHz 653μW fractional-N ADPLL that achieves −242dB FOM in 65nm CMOS for 2.4GHz ISM band applications and breaks the −240 dB FOM barrier of sub-mW fractiona-NADPLLs.
Journal ArticleDOI
A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS
Hanli Liu,Zheng Sun,Dexian Tang,Hongye Huang,Tohru Kaneko,Zhijie Chen,Wei Deng,Rui Wu,Kenichi Okada +8 more
TL;DR: A DPLL-based ADC with a digital-to-analog converter feedback greatly improves the ADC dynamic range, which improves the RX sensitivity and interference tolerance, and maximally reducing the required radio frequency and analog front-end components in RX.