Showing papers in "IEEE Transactions on Components, Packaging and Manufacturing Technology in 2011"

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

Abstract: We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic RLGC equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.

Die Attach Materials for High Temperature Applications: A Review

Abstract: The need for high power density and high temperature capabilities in today's electronic devices continues to grow. More robust devices with reliable and stable functioning capabilities are needed, for example in aerospace and automotive industries as well as sensor technology. These devices need to perform under extreme temperature conditions, and not show any deterioration in terms of switching speeds, junction temperatures, and power density, and so on. While the bulk of research is performed to source and manufacture these high temperature devices, the device interconnect technology remains under high focus for packaging. The die attach material has to withstand high temperatures generated during device functioning and also cope with external conditions which will directly determine how well the device performs in the field. This literature work seeks to review the numerous research attempts thus far for high temperature die attach materials on wide band gap materials of silicon carbide, gallium nitride and diamond, document their successes, concerns and application possibilities, all of which are essential for high temperature reliability.

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

Abstract: In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

High-Frequency Modeling of TSVs for 3-D Chip Integration and Silicon Interposers Considering Skin-Effect, Dielectric Quasi-TEM and Slow-Wave Modes

Abstract: Through-silicon vias (TSVs) in low, medium and high resistivity silicon for 3-D chip integration and interposers are modeled and thoroughly characterized from 100 MHz to 130 GHz, considering the slow-wave, dielectric quasi-TEM and skin-effect modes. The frequency ranges of these modes and their transitions are predicted using resistivity-frequency domain charts. The impact of the modes on signal integrity is quantified, and three coaxial TSV configurations are proposed to minimize this impact. Finally, conventional expressions for calculating the per-unit-length circuit parameters of transmission lines are extended and used to analytically capture the frequency dependent behavior of TSVs, considering the impact of the mixed dielectric (silicon dioxide-silicon-silicon dioxide) around the TSVs. Excellent correlation is obtained between the analytical calculations using the extended expressions and electromagnetic field simulations up to 130 GHz. These extended expressions can be implemented directly in electronic design automation tools to facilitate performance evaluation of TSVs, prior to system design.

PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models

Abstract: The impedance of a power-distribution network (PDN) in three-dimensionally stacked chips with multiple through-silicon-via (TSV) connections (a 3D TSV IC) was modeled and analyzed using a power/ground (P/G) TSV array model based on separated P/G TSV and chip-PDN models at frequencies up to 20 GHz. The proposed modeling and analysis methods for the P/G TSV and chip-PDN are fundamental for estimating the PDN impedances of 3D TSV ICs because they are composed of several chip-PDNs and several thousands of P/G TSV connections. Using the proposed P/G TSV array model, we obtained very efficient analyses and estimations of 3D TSV IC PDNs, including the effects of TSV inductance and multiple-TSV inductance, depending on P/G TSV arrangement and the number of stacked chip-PDNs of a 3D TSV IC PDN. Inductances related to TSVs, combined with chip-PDN inductance and capacitance, created high upper peaks of PDN impedance, near 1 GHz. Additionally, the P/G TSV array produced various TSV array inductance effects on stacked chip-PDN impedance, according to their arrangement, and induced high PDN impedance, over 10 GHz.

Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects

Abstract: 3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems. This paper presents an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects. The model is correlated with measurement results for validation. Parametric analysis of TSV capacitance is performed on several physical and material parameters. Design guidelines are proposed for TSVs used in signal and power distribution networks as well as for TSVs as variable capacitors. A 3-D power distribution network is simulated to show the effect and importance of the voltage-dependent TSV MOS capacitance.

Organic Packages With Embedded Phased-Array Antennas for 60-GHz Wireless Chipsets

Abstract: A multilayer organic package with embedded 60-GHz antennas and fully integrated with a 60-GHz phased-array transmitter or receiver chip is demonstrated. The package includes sixteen phased-array antennas, an open cavity for housing the flip-chip attached RF chip, and interconnects operating at DC-66 GHz. The 28 mm 28 mm ball grid array package is manufactured using printed circuit board processes and uses a combination of liquid-crystal polymer and glass-reinforced laminates, allowing excellent 60-GHz interconnect and antenna performance. The measured return loss and gain of each antenna from 56 to 66 GHz are and , respectively. Finally, the packaged transmitter and receiver chipsets, each working with a heat sink, have demonstrated beam-steered, non-line-of-sight links with data rates up to 5.3 Gb/s using 16-quadrature amplitude modulation single-carrier and orthogonal frequency division multiplexing schemes.

Electrical-Thermal Co-Simulation of 3D Integrated Systems With Micro-Fluidic Cooling and Joule Heating Effects

Abstract: In this paper, the electrical-thermal co-simulation of 3D systems with Joule heating, fluidic cooling and air convection effects is proposed. The finite-volume method formulations of voltage distribution equation, heat equations for both fluid flow and solid medium with nonuniform mesh are explained in detail. Based on the proposed iterative co-simulation method, package temperature distribution and voltage drop with Joule heating and fluidic cooling effects can be estimated. Several packaging examples are simulated and the results show that with micro-channel fluidic cooling in high power density 3D integrated packages, the thermal effect on voltage drop is reduced by 10% which is much less than that of using a traditional heat sink.

Parameters Variability Effects on Multiconductor Interconnects via Hermite Polynomial Chaos

Abstract: This paper focuses on the derivation of an enhanced transmission-line model allowing the stochastic analysis of a realistic multiconductor interconnect. The proposed model, which is based on the expansion of the well-known telegraph equations in terms of orthogonal polynomials, includes the variability of geometrical or material properties of the interconnect due to uncertainties like fabrication process or temperature. A real application example involving the frequency-domain analysis of a coupled microstrip and the computation of the parameters variability effects on the transmission-line response concludes this paper.

Characterization of Lead-Free Solder and Sintered Nano-Silver Die-Attach Layers Using Thermal Impedance

Abstract: Since a die-attach layer has a significant impact on the thermal performance of a power module, its quality can be characterized using thermal performance. In this paper, a measurement system for thermal impedance is developed to evaluate three die-attach materials. Thanks to its high temperature sensitivity (10 mV/°C), the gate-emitter voltage of an insulated gate bipolar transistor (IGBT) is used as the temperature-sensitive parameter. The power dissipation in the IGBT remains constant by a feedback loop, regardless of the junction temperature. Experimental results show that the sample using sintered nano-silver for the die-attach has 12.1% lower thermal impedance than the samples using SAC305 and SN100C solders. To check the degradation of the die-attachment, six samples using three die-attach materials were thermally cycled from -40 to 125°C. The experimental results show that, after 500 cycles, the thermal impedance of SAC305 samples and SN100C samples is increased by 12.9% and 13.3%, respectively, which are much higher than that of the sample using the sintered nano-silver for the die-attach (3.1%).

High-Speed Design and Broadband Modeling of Through-Strata-Vias (TSVs) in 3D Integration

Abstract: Through-strata-via (TSV) technology emerges as the key technology to enable 3D integration. In this paper, 3D electromagnetic field solvers and analytic circuit simulators are employed to study and model TSV electrical performance. Performance of simple TSV structure is analyzed in the time domain and frequency domain. Performance impacts of various TSV configurations are evaluated. A broadband TSV equivalent circuit model is developed for 3D circuit design. Key results include: 1) excellent TDR/TDT behavior and wide open eye diagram with ultra low bit error rate can be achieved with a given TSV configuration; 2) TSV performance depends on TSV configurations (e.g., circular, rectangular, square, tapered, and annular shapes as well as their scaling), but a wide range of different TSV configurations can be optimized with acceptable TSV performance; and 3) broadband TSV equivalent circuit models can be established and used for 3D circuit design with electronic design automation tools.

Terahertz Characterization of Dielectric Substrates for Component Design and Nondestructive Evaluation of Packages

Abstract: In this paper, terahertz (THz) characterization of dielectric substrates, THz planar and quasi-optical components, THz probing of planar devices, and THz nondestructive evaluation (NDE) are demonstrated. In particular, the goals of this paper are: 1) characterization of dielectric substrates for THz packaging applications; 2) design, fabrication, and evaluation of THz components built using some of these dielectric substrates; and 3) the use of the dielectric characterization approach and dielectric properties in NDE of electronic packages. The background theory for characterizing dielectric substrates using THz time-domain signals is provided. The Nelder and Mead modified simplex optimization algorithm is utilized in order to extract the dielectric properties of different packaging materials encompassing organic, inorganic, and composite materials. A planar THz power splitter, a dielectric probe, and a low-cost polymer-based quasi-optical band-stop interference filter are demonstrated. THz NDE of electronics packages is demonstrated for packaging delamination and moisture ingression in dielectric films.

Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs

Abstract: This paper focuses on low-power and low-slew clock network design and analysis for through-silicon via (TSV) based three-dimensional stacked ICs (3D ICs). First, we investigate the impact of the TSV count and the TSV resistance-capacitance (RC) parasitics on clock power consumption. Several techniques are introduced to reduce the clock power consumption and slew of the 3D clock distribution network. We analyze how these design factors affect the overall wire length, clock power, slew, and skew in 3D clock network design. Second, we develop a two-step 3D clock tree synthesis method: 1) 3D abstract tree generation based on the three-dimensional method of means and medians (3D-MMM) algorithm; 2) buffering and embedding based on the slew-aware deferred-merge buffering and embedding (sDMBE) algorithm. We also extend the 3D-MMM method (3D-MMM-ext) to determine the optimal number of TSVs to be used in the 3D clock tree so that the overall power consumption is minimized. Related SPICE simulation indicates that: 1) a 3D clock network that uses multiple TSVs significantly reduces the clock power compared with the single-TSV case, 2) as the TSV capacitance increases, the power savings of a multiple-TSV clock network decreases, and 3) our 3D-MMM-ext method finds a close-to-optimal design point in the “TSV count versus power consumption” tradeoff curve very efficiently.

Flow Boiling of R134a in a Multi-Microchannel Heat Sink With Hotspot Heaters for Energy-Efficient Microelectronic CPU Cooling Applications

Abstract: This paper focuses on two-phase flow boiling of refrigerant R134a inside a copper multi-microchannel heat sink for microelectronic central processing unit cooling applications. The heat sink is composed of 100 parallel microchannels, 100 μm wide, 680 μm high, and 15 mm long, with 72-μm-thick fins separating the channels. The base heat flux was varied from 2.57 to 189 W/cm2 and the mass flux from 205 to 1000 kg/m2s, at a nominal saturation temperature of 63°C. Over 40 000 local heat transfer coefficients were measured at 35 locations using local heaters and temperature sensors, for which different heat transfer trends were identified. The main ones were that the heat transfer coefficient increased with heat flux and was independent of mass flow rate. Heat transfer coefficients as high as 270 000 W/m K (relative to the base area) were reached, keeping the chip under 85°C with a maximum of 94 kPa of pressure drop, for no inlet subcooling and a coolant flow rate of 1000 kg/m2s.

Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling

Abstract: In this paper, we present analytical models for fast estimation of coupling capacitance of square-shaped through-silicon vias (TSVs) in three-dimensional integrated circuits (3D ICs). Errors between our model and Synopsys Raphael simulation on regular TSV structures remain less than 6.03% while the computation time of our model for capacitance estimation is negligible. We also develop a simple capacitance estimation technique to extract TSV-to-TSV coupling capacitance in general layouts. Average errors between our model and Raphael simulation on random TSV structures is 5.06%-8.24%, and maximum errors remain less than 18.91% which is tolerable for fast capacitance estimation in computer-aided design area.

Dual- and Triple-Band Wilkinson Power Dividers Based on Composite Right- and Left-Handed Transmission Lines

Abstract: This paper presents dual- and triple-band equal-split Wilkinson power dividers (WPDs) based on composite right- and left-handed transmission lines. Good isolation between output ports and impedance matching at input ports are achieved simultaneously at all pass-band frequencies for both dual- and triple-band WPDs. The theoretical closed-form design equations are derived, and the design allows a wide range of flexibility for the allocations of the passbands. To verify the proposed design, two prototypes are fabricated and measurements show good agreement with simulated data. The first design is a triple-band WPD with passbands centered at 0.8, 1.3, and 1.85 GHz, and the second one is a dual-band WPD with passbands centered at 0.7 and 1.5 GHz. The triple-band divider has a length of 0.66 wavelengths in the substrate and is more compact comparing to traditional WPDs. The dual-band power divider is designed to have a wide fractional bandwidth with more than 20% at the lower passband and 41% at the upper passband. Measurements also show a good insertion loss at each input port, which is less than 3.6 dB at the center of each passband.

Influence of Bosch Etch Process on Electrical Isolation of TSV Structures

Abstract: Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops.

Ultrathin Thermoelectric Devices for On-Chip Peltier Cooling

Abstract: The efficient usage of thermoelectric (TE) devices for microelectronics cooling application requires investigation and remedy of various obstacles such as integration of these devices with electronic package, parasitic contact resistances, and utilization of appropriate current pulses. We develop a computational model to investigate the effect of steady state and transient mode of operation of ultrathin thermoelectric cooler (TEC) devices on hot-spot cooling considering the effect of crucial thermal and electrical contact resistances. Our analysis shows that the transient pulses can be very effective in reducing the hot-spot temperature by 6-7°C in addition to the cooling achieved by the steady state current through the TEC device. We correlate the important characteristics of the transient temperature behavior of hot-spot under the TEC operation such as the maximum temperature drop (ΔTmax), time taken to achieve ΔTmax and temperature overshoot after turning off pulse current with the electrical and thermal contact resistances and Seebeck coefficient of the TE material. It has been observed that thermal and electrical contact resistances play a very crucial role in the performance of TEC devices as high values of these resistances can significantly diminish the effect of Peltier cooling during steady state operation. The effect of these parasitic resistances is even higher for the transient cooling of hot-spots by the pulsed current through the TEC device. High Seebeck coefficient of TE materials is desirable as it increases the figure of merit of TE devices. However, cooling capabilities of heat sink may become bottleneck to realize the benefits of very high Seebeck coefficient as the back heat flow from the hot side to cold side of TEC device diminishes the degree of cooling achieved by these ultrathin TECs.

TSV Technology for Millimeter-Wave and Terahertz Design and Applications

Abstract: The through silicon via (TSV) technology provides a promising option to realize a compact millimeter-wave (mmW) and terahertz (THz) system with high performance. As the fundamental elements in this system, transmission lines (T-lines) and interconnects are very important and therefore studied in this paper. A TSV-based substrate integrated waveguide (SIW) is also characterized. The results show that, the T-lines and interconnects are viable at frequencies lower than ~150 GHz whereas SIW can operate relatively well up to 300 GHz. In addition, two mmW components, i.e., a hairpin filter and a patch antenna, are designed by the TSV technology. Results of all the above passive components indicate that the low-resistivity silicon is the main cause of the total loss. Afterwards, two novel TSV-based topologies are proposed to efficiently integrate an antenna with active circuits for the mmW and THz applications.

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

Abstract: Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 μm in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up plating method is used to fill the TSVs with Cu. In order to fill the TSVs from bottom, the TSVs are first sealed from the bottom by plated Cu with plating current of 1 A. The plated Cu is used as a seed layer and bottom-up plating is then conducted with plating current of 0.1 A. Good filling without voids or with only tiny voids has been achieved. Electroless nickel/immersion gold is plated on top of the TSVs as under bump metallurgy pads. On the top Si die, Cu pillars/Sn caps with 16 μm in diameter and 25 μm in pitch are fabricated with electroplating method. After chip stacking, interconnections are formed between them through the solder microbumps and the TSVs.

Passive UHF RFID Packaging With Electromagnetic Band Gap (EBG) Material for Metallic Objects Tracking

Abstract: Passive ultrahigh frequency (UHF) radio frequency identification (RFID) is a promising technology for products tracking in logistics or routing packages in supply chain. However, passive UHF RFID tag's performance degrades a lot when it is placed near metal plane or water surface. Many designs like microstrip antenna and ferrite material antenna have been used to solve this metal–water problem. But their usage is limited by narrow bandwidth and low antenna gain. The electromagnetic band gap (EBG) material which exhibits a unique forbidden band gap at certain frequency offers a potential solution to solve this metal–water problem. In this paper, we disclosed a new method using EBG material to insulate the UHF RFID tag from backside objects, so that the tag could still work on metallic surface. The design of EBG material for UHF RFID which operates at 915 MHz under federal communications commission regulation was discussed in this paper. The simulation results showed that the EBG RFID tag can be read on metal. The measurement results indicated that the read range of RFID tag with EBG substrate is up to 9 m on metal surface.

Design of Integrated Nanostructured Wicks for High-Performance Vapor Chambers

Abstract: The performance of passive phase-change cooling devices, such as vapor chambers or heat pipes, may be significantly enhanced by exploiting the superior thermal properties of carbon nanotube (CNT) arrays. The potential for large reductions in overall package resistance with the use of high-conductivity wick materials enhanced with CNT nanostructures is investigated. While such nanostructured wicks feature very small pore sizes that support high capillary pressures, it is shown that the high fluid flow resistance through these dense arrays prevents their use as the lone fluid transport mechanism. It is proposed that evaporator surfaces comprised of nanostructured wicks fed by interspersed conventional wick materials (such as sintered powders) can provide the required permeability for fluid flow while simultaneously decreasing the effective evaporator thermal resistance. Optimization of wicks with integrated sintered and nanostructured areas requires a study of the trade-offs between the greater permeability of the sintered materials and the greater capillary pressure and thin-film evaporation area offered by the nanostructures. A numerical model is developed to estimate the thermal resistance of the evaporator region compared to that of a homogeneous sintered powder wick. The inputs needed for this model include the permeability and the capillary pressure in the two regions. A parametric study is conducted as a function of the ratio of conduction and evaporative resistances for the nanostructured and sintered regions. For a given heat input, the optimal liquid-feeding geometry that minimizes thermal resistance is obtained. In the best cases, the thermal resistance is reduced by a factor of thirteen through the use of the integrated nanostructured wicks compared to the resistance of a homogeneous sintered powder wick.

Analysis of Theoretical Limits of Forced-Air Cooling Using Advanced Composite Materials With High Thermal Conductivities

Abstract: Cooling systems take a significant portion of the total mass and/or volume of power electronic systems. In order to design a converter with high power density, it is necessary to minimize the converter's cooling system volume for a given maximum tolerable thermal resistance. This paper theoretically investigates whether the cooling system volume can be significantly reduced by employing new advanced composite materials like isotropic aluminum/diamond composites or anisotropic highly orientated pyrolytic graphite. Another strategy to improve the power density of the cooling system is to increase the rotating speed and/or the diameter of the fan, which is limited by increasing power consumption of the fan. Fan scaling laws are employed in order to describe volume and thermal resistance of an optimized cooling system (fan plus heat sink), resulting in a single compact equation dependent on just two design parameters. Based on this equation, a deep insight into different design strategies and their general potentials is possible. The theory of the design process is verified experimentally for cooling a 10 kW converter. Further experimental results showing the result of the operation of the optimized heat sink are also presented.

Efficient Implicit–Explicit Time Stepping Scheme With Domain Decomposition for Multiscale Modeling of Layered Structures

Abstract: An efficient time-domain technique is proposed for multiscale electromagnetic simulations of layered structures. Each layer of a layered structure is independently discretized by finite elements, and the discontinuous Galerkin method is employed to stitch all discretized subdomains together. The hybrid implicit-explicit Runge-Kutta scheme combined with subdomain-based Gauss-Seidel iteration is employed for time stepping. The block Thomas algorithm is utilized to accelerate time stepping for block tri-diagonal systems, which are frequently encountered in discretized layered structures. Numerical examples demonstrate that the proposed method is efficient in simulating multiscale layered structures.

Solder Joint Inspection Method for Chip Component Using Improved AdaBoost and Decision Tree

Abstract: To improve the performance of automatic optical inspection (AOI), a new inspection method for chip component of mounted components on printed circuit boards is developed. In this paper, the inspection procedure is divided into training stage and test stage. In the training stage, first, the solder joint is divided into several sub-regions according to priori knowledge, second, various features in every sub-region are extracted, then, for every sub-region the optimal features are selected with an improved AdaBoost by evaluating their classification ability and independency, finally, the classifier for every sub-region is established with the selected features by training a number of samples. In the test stage, after image acquirement the inspection of a solder joint consists of region division, critical features extraction, classification of sub-regions, and defect diagnosis. The former three steps are executed based on the training results, and in the last step a new defect binary decision tree based on classification and regression tree is used to determine the final defect type. To evaluate the performance of the proposed method, various types of solder joints were inspected by an AOI system which integrates with the proposed method. The inspection results have verified the effectiveness of this method in terms of speed and recognition rate.

Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System

Abstract: In this paper, we present a methodology for characterization and repair of signal degradation in through-silicon-vias (TSVs) in 3-D integrated circuits (ICs). The proposed structure can detect the signal degradation through TSVs due to resistive shorts in liner oxide and variations in resistance of TSV due to weak open and/or bonding resistance. For TSVs with moderate signal degradations, the proposed structure reconfigures itself as signal recovery circuit to maintain signal fidelity. This allows electrical repair of TSVs with moderate defects leading to better design yield and system functionality. This paper presents the design of the test and recovery structure and demonstrates their effectiveness through stand alone simulations as well as in a full-chip physical design of a 3-D IC.

Wafer-Level Cu/Sn to Cu/Sn SLID-Bonded Interconnects With Increased Strength

Abstract: Wafer level Cu-Sn solid liquid interdiffusion (SLID) bonding of interconnects was achieved by bonding two-layered Cu/Sn structures to each other. The bonded interconnects were investigated by mechanical, electrical and microscopic techniques. The Cu-Sn SLID interconnects were created by wafer-level bonding at 260°C. The bonded interconnects show shear strength of 45 MPa and a resistance of the order 100 mΩ . A major advantage of the Cu/Sn to Cu/Sn bonding scenario is to avoid the dynamic wetting of molten Sn to Cu, and simply replace with a liquid to liquid integration. Furthermore, the Sn overflow problem in a Cu/Sn SLID system was successfully addressed by designing a margin of 15 μm at the Cu pads to tolerate any Sn spreading. The uniformity requirement for electroplated Cu-Sn layers, which is crucial for achieving successful wafer-level bonding, is discussed. This wafer-level Cu-Sn SLID bonding process is a promising technique for 3-D assembly and packaging.

Thermal Performance of Microchannels With Wavy Walls for Electronics Cooling

Abstract: Wavy walls are investigated in this paper as a passive scheme to improve the heat transfer performance of low-Reynolds-number laminar flows in microchannel heat sinks for electronics cooling applications. 3-D laminar fluid flow and heat transfer characteristics in microchannels with wavy walls are numerically studied for a 500-μm hydraulic diameter channel by varying the wavy feature amplitude at different Reynolds numbers (10, 20, 50, and 100). In addition, flow measurements are made using a micrometer-resolution particle image velocimetry technique for understanding the fundamentals of fluid flow in the wavy-walled microchannels for the considered Reynolds numbers. Based on the comparison with straight channels, it was found that wavy channels can provide improved heat transfer performance while keeping the pressure drop within acceptable limits. Accordingly, wavy channels are to found to provide an improvement of up to 26% in the overall performance (which includes the effect of wall waviness on heat transfer, pressure drop, and surface area) compared to microchannels with straight walls for the same pumping power and hence are attractive candidates for cooling of future electronics.

Solutions Strategies for Die Shift Problem in Wafer Level Compression Molding

Abstract: Die shift problem that arises during the wafer molding process in embedded micro wafer level package fabrication was systematically analyzed and solution strategies were developed A methodology to measure die shift was developed and applied to create maps of die shift on an 8 inch wafer A total of 256 dies were embedded in an 8 inch mold compound wafer using compression molding Thermal and cure shrinkages of mold compound are determined to be the primary reasons for die shift in wafer molding Die shift value increases as the distance from the center of the wafer increases Pre-compensation of die shift during pick and place is demonstrated as an effective method to control die shift Applying pre-compensation method 99% of dies can be achieved to have die shift values of less than 40 μm Usage of carrier wafer during wafer molding reduces the maximum die shift in a wafer from 633 μm to 79 μm Die area/package area ratio has a strong influence on the die shift values Die area/package area ratios of 081, 049, and 025 lead to maximum die shift values of 26, 76, and 97 μm, respectively Wafer molding using low coefficient of thermal expansion (7 × 10-6/°C) and low cure shrinkage (0094%) mold compounds is demonstrated to yield maximum die shift value of 28 μm over the whole 8 inch wafer area

Design of Microstrip-to-Microstrip Via Transition in Multilayered LTCC for Frequencies up to 67 GHz

Abstract: A wide-band microstrip-to-microstrip via transition proposed for connecting an integrated circuit chip and an antenna array on the opposite sides of a multilayered low-temperature co-fired ceramic substrate is investigated in this paper. To facilitate the design, it is decomposed into external and internal segments, which consist of two microstrip-to-via transitions and a multilayered through-hole via with four ground vias, respectively. The equivalent impedance of the internal segment is carefully calculated from the lump-circuit model extracted by Ansoft Q3D, and verified by high-frequency structure simulation (HFSS). The S-parameters of external segments are simulated by HFSS for impedance matching, thereby obtaining the appropriate physical parameters. The physical mechanisms that result in the insertion loss are explored in detail, and the effects of via diameter are also investigated for the reduction of insertion loss. By combining the designs of the external and internal segments, the simulated S-parameters demonstrated that the overall return loss level was above 20 dB within 57-67 GHz spectrum and insertion loss was better than 0.48 dB from d.c. up to 67 GHz. Coherent results between simulation and measurement were also obtained with a back-to-back transition structure.