Showing papers by "Dinesh K. Sharma published in 2014"

Review and Analysis of Solar Photovoltaic Softwares

Abstract: In this paper we have presented all the Photovoltaic simulation software that is available in market for commercial application as well as for educational and research purpose till date. For this an extensive search was made to providing all the details of Photovoltaic simulation software presented in this paper. The investigated simulation software’s were evaluated according to the following criteria. P1 their commercial and educational availability and cost P2 their working platform P3 their working capacities P4 their scope and output P5 their updatability

Design considerations for high-CMRR low-power current mode instrumentation amplifier for biomedicai data acquisition systems

Abstract: This paper presents a design procedure for practical implementation of current mode instrumentation amplifier (CMIA). The design flow highlights the major tradeoffs in the design of CMIA, enabling a designer to optimize the design as per the desired critical performance specifications. PSRR analysis of the implemented CMIA is also presented. The target specifications comprise a CMRR better than 100 dB without using choppers and without trimming, programmable bandwidth, accurate and stable gain, rail to rail output swing with 100 pF capacitive load driving capability while minimizing the power dissipation and the area. The gain is programmable from 34 dB to 60 dB and the bandwidth is programmable upto 10 kHz. The thermal noise floor is 145 nV/√Hz. The presented chopper-less CMIA has been designed and optimized in 180 nm mixed-mode CMOS technology. It features high CMRR of > 112 dB in the presence of 4.5 mV input offset voltage without any chopper modulator.

Ultra-low power neural stimulator for electrode interfaces

Abstract: Power loss at the output stage of conventional constant current neural stimulators is notably high. This is particularly disadvantageous for applications in implantable systems where power budget is limited. We present a novel electrical stimulator architecture for significantly reduced power loss and low noise operation. The system generates a calibrated output voltage profile for driving electrode impedance with an approximate biphasic current stimulation. The stimulator utilizes switched-capacitor output driver stage and low speed operations for substantial reduction in power loss. The hardware is capable of generating on-demand clock signals for appropriate switching events through a feedback mechanism. The self-clocking ultra-low power stimulator front-end and its controller exhibits quasi-stable quiescent power consumption of 3.75 μW and raw efficiency up to 98%. The low power stimulator architecture consumes nearly 70% less power than conventional linear mode stimulators and half of the reported state-of-the art design. Output peak-to-peak noise down to 20 mV is achieved through this design. Demonstrations are shown with RC impedance, platinum-iridium electrode in saline solution and in-vivo somatosensory cortex stimulation.

Drain extended MOS device design for integrated RF PA in 28nm CMOS with optimized FoM and ESD robustness

Abstract: This paper explores drain extended MOS (DeMOS) device design guidelines for an area scaled, ESD robust integrated radio frequency power amplifier (RF PA) for advanced system-on-chip applications in 28nm node CMOS. Simultaneous improvement of device-circuit performance and ESD robustness is discussed for the first time. By device design optimization a 45% increase in gain and 25% in power-added efficiency of RF PA at 1GHz, and 5× improvements in ESD robustness are reported experimentally.

A comparison of S-shaped and U-shaped optical fiber sensors

Abstract: S-shaped optical fiber sensors were fabricated and its sensing potential was compared with U-bend sensors. Evanescent wave absorbance and refractive index sensitivity of S-bend were found to be 1.8-fold and 1.5-fold higher than U-bend.

Implementation of high performance Readout Integrated Circuit

Abstract: The Readout Integrated Circuit (ROIC) consists of charge integration, charge to voltage conversion, Pixel voltage multiplexing, signal transfer and amplification stage. The control circuit manages all the sequential events from charge integration to amplification stage. The large dynamic range requirement is the most challenging aspect in modern CMOS process. The infrared (IR) detectors looks for the integration of large charge handling capacity more than 10Me̅, at the same time sensitive enough to detect signals just above the noise floor of better than 900e̅. The ROIC's uses a capacitor along with active elements for signal integration and processing. The amount of charge collected is defined by the charge handling capacity and limited by the size of integrating capacitor. In addition to this, signal processing also requires multiple large capacitors, which lead to complex tradeoffs, as all these must fit within the pixel size dictated by the requirements of IR detectors. Detectors operate with relatively high bias voltage, which further complicates interface design and silicon process selection. This paper discusses design optimization and implementation of direct injection ROIC. The 4×4 array ROIC test chip has 10 Me̅ charge handling capacity , maximum pixel pitch of 30μm, snapshot mode of operation, variable integration time, 3 Mega pixels per second (Mpps) readout rate and readout noise of 350e̅ reported at ambient temperature for the first time.

A Review of Solar Energy: Potential, Status, Targets and Challenges in Rajasthan

Abstract: Rajasthan has a huge potential of solar energy, the climatic conditions of state makes it ideal for capturing the solar rays in sufficiency. The climate of Rajasthan is semi-arid; the desert of Thar is spreads on the 66.66 % of total area of state. These climatic specialties makes it suitable to receive almost 300325 sunny days in a year and 6-6.4kwh/m/ sun radiation per day, which is second highest amount of sun radiation all over the world. The average temperature of western cities of Rajasthan is between 35-40 degree, and in summer, it reaches above 45 degree. The availability of solar energy in Rajasthan is 6 to 7 kw/km, which provides the potential of 100000MW electricity yearly, out of which only 442.25 MW is currently being produced. Certainly, it is not a satisfactory situation. This paper describes the potential, status, targets and challenges in solar energy in Rajasthan. Keywords-solar photovoltaic, solar potential, sun radiation Abbreviations: SEEZ Solar Energy Enterpirses Zone ISCC Intregrated Solar Combined CYCLE GBI Generation Based Incentive Scheme RERC Rajasthan Electricuty Regulatory Commission RPO Renewalble Procurment Obligation RECL Rural Electrification Corporation Ltd. REC Renewable Energy Certificate RREC Rasjathan Renewable Energy Corporation PV Photovoltaic MW Megha Watt TW Tera Watt US United State USA United State of America

Dielectric Protected Fiber-Optic Nano-Biosensensor

Abstract: We demonstrated biosensing on gold nanoparticle (GNP) and silicon nitride (SiNx) coated localized surface plasmon resonance based fiber-optic probe. The SiNx over-layer protects the GNPs from deteriorating ageing effects and allows long term usage of sensors.

Efficient implementation of high performance Read out Integrated Circuit

Abstract: The Read out Integrated Circuit (ROIC) consists of charge integration, charge to voltage conversion, Pixel voltage multiplexing, signal transfer and amplification stages. The control circuit manages all the sequential events from charge integration to amplification stage. Design and optimization of ROIC for hybrid detectors has multidimensional challenges including requirement for long simulation time for specified 25 to 100 Hz frame rate. Normally useful simulation data starts after 3 frame time and minimum transient simulation required for the same is 10 ms for 100 Hz frame rate. The simulation time for each input condition is ∼120 hours with traditional simulators. ROIC critical specifications i.e. charge handling capacity and linearity has to be checked before chip integration to Pad. The linearity check requirs at least six point simulation and lead to 1 month simulation time on state of the art servers. Fast spice simulator with set_sim_level 5 has been used for the first time and reduces simulation time to 230 hours on same machine for the linearity simulation of ROIC. Test chip 4×4 ROIC has been fabricated using UMC 180 nm CMOS process and experimental results matched within 0.4% variation w.r.t. fast spice simulation results.