Other affiliations: Purdue University
Bio: Dinesh Somasekhar is an academic researcher from Intel. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 14, co-authored 54 publications receiving 989 citations. Previous affiliations of Dinesh Somasekhar include Purdue University.
Papers published on a yearly basis
TL;DR: Methods for estimating leakage at the circuit level are outlined and a heuristic and exact algorithms to accomplish the same task for random combinational logic are proposed.
Abstract: Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I/sub D/DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.
TL;DR: Differential current switch logic (DCSL) as mentioned in this paper is a new logic family for implementing clocked CMOS circuits, which achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree.
Abstract: Differential current switch logic (DCSL), a new logic family for implementing clocked CMOS circuits, has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree. DCSL circuits are capable of implementing high complexity high fan-in gates without compromising gate delay. Automatic lock-out of inputs on completion of evaluation is a novel feature of the circuit. Three forms of DCSL circuits have been developed with varying benefits in speed and power. SPICE simulations of circuits designed using the 1.2 /spl mu/m MOSIS SCMOS process indicate a factor of two improvement in speed and power over comparable DCVS gates for moderate tree heights.
••01 Jun 1999
TL;DR: The state dependence of leakage can be exploited to obtain modest leakage savings in CMOS circuits, but one can modify circuits considering state dependence and achieve larger savings.
Abstract: The state dependence of leakage can be exploited to obtain modest leakage savings in CMOS circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low leakage state and insert leakage control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone.
•05 Apr 2002
TL;DR: In this article, a power management device and static random access memory (SRAM) architecture with dynamic supply voltages are proposed to reduce active power leakage in SRAM cells, where a low level supply voltage is applied to the source line connected to the cell to maintain the data stored in the cell.
Abstract: A power management device and static random access memory (SRAM) architecture with dynamic supply voltages reduce active power leakage in SRAM cells. When a cell is inactive, a low level supply voltage is applied to the source line connected to the cell to maintain the data stored in the cell. However, before a cell is accessed (e.g., during a read or write operation), the source line is raised to a high level supply voltage.
•03 Oct 2001
TL;DR: Open bit line dynamic random access memory (DRAM) architectures as discussed by the authors use a multiple layer bit line configuration to reduce coupling between switching bit lines in the device, and dummy signal injection techniques are also provided for reducing the effect of word line to bit line coupling in the DRAM device.
Abstract: An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.
29 Apr 2003
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.
••07 Jun 2004
TL;DR: Simulation experiments show that the critical speed slowdown results in up to 5% energy gains over a leakage oblivious dynamic voltage scaling, and the Procrastination scheduling scheme extends the sleep intervals to 5 times, resulting in an additional 18% energy gain, while meeting all timing requirements.
Abstract: A five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also causes increased leakage energy drain by lengthening the interval over which a computation is carried out. Therefore, for minimization of the total energy, one needs to determine an operating point, called the critical speed. We compute processor slowdown factors based on the critical speed for energy minimization. Procrastination scheduling attempts to maximize the duration of idle intervals by keeping the processor in a sleep/shutdown state even if there are pending tasks, within the constraints imposed by performance requirements. Our simulation experiments show that the critical speed slowdown results in up to 5% energy gains over a leakage oblivious dynamic voltage scaling. Procrastination scheduling scheme extends the sleep intervals to up to 5 times, resulting in up to an additional 18% energy gains, while meeting all timing requirements.
••01 Dec 2000
TL;DR: A simple equation for estimating static power consumption at the architectural level and suggest opportunities for static power optimization, including reducing the total number of devices, partitioning the design to allow for lower supply voltages or slower, less leaky transistors.
Abstract: Static power dissipation due to transistor leakage constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the contribution will increase rapidly, reaching one half of total power dissipation within three process generations. Developing power efficient products will require consideration of static power in the earliest phases of design, including architecture and microarchitecture definition. We propose a simple equation for estimating static power consumption at the architectural level: P/sub static/=V/sub CC//spl middot/N/spl middot/k/sub design//spl middot/I/spl circ//sub leak/, where V/sub CC/ is the supply voltage, N is the number of transistors, k/sub design/ is a design dependent parameter, and I/spl circ//sub leak/ is a technology dependent parameter. This model enables high-level reasoning about the likely static power demands of alternative microarchitectures. Reasonably accurate values for the factors within the equation may be obtained directly from the high-level designs or by straightforward scaling arguments. The factors within the equation also suggest opportunities for static power optimization, including reducing the total number of devices, partitioning the design to allow for lower supply voltages or slower, less leaky transistors, turning off unused devices, favoring certain design styles, and favoring high bandwidth over low latency. Speculation is also examined as a means to employ slower transistors without a significant performance penalty.
10 Aug 1998
TL;DR: Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.
Abstract: Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by IISPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.
21 Jan 2003
TL;DR: In this article, a switch, switched architecture and process for transferring data through an FCAL switch is disclosed, which uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch.
Abstract: A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.