Silicon carbide single-photon sources: challenges and prospects

Silicon carbide (SiC) MOSFETs still exhibit higher drifts of the threshold voltage than comparable silicon devices due to charge trapping, especially regarding small time scales. Understanding this behavior and the consequences in application relevant conditions is therefore of high research interest. Since charge trapping at different defects close to the SiC/ SiO2 interface and in the bulk oxide is strong bias and temperature-dependent, the phenomenon is referred to as bias temperature instability (BTI). It has been shown that drifts caused by BTI vary both in transient shape and magnitude for commercially available devices. These differences arise from defect densities and properties in the respective technologies. A physical model together with defect parameters that explain the charge transfer reactions at the defects is essential to understand all peculiarities of the transient degradation. In this work, we use a novel method to semiautomatically extract defect parameters within a two-state nonradiative multiphonon model framework. Our work reveals properties of defects responsible for shifts of the threshold voltage for both short-term ac and long-term dc stress conditions which are accurately reproduced for three different DMOS technologies. Our calibrated simulation framework is further used to extrapolate device degradation at operation relevant ac bias conditions to typical device lifetimes.

Physical Modeling of Charge Trapping in 4H-SiC DMOSFET Technologies

In this article, a method for evaluating the implications of threshold voltage ( VTH ) drift from gate voltage stress in SiC MOSFET s is presented. By exploiting the Miller coupling between two devices in the same phase leg, the technique uses the shoot-through charge from parasitic turn- on to characterize the impact of bias temperature instability (BTI)-induced VTH shift. Traditional methods of BTI characterization rely on the application of a stress voltage without characterizing the implication of the VTH shift on the switching characteristics of the device in a circuit. Unlike conventional methods, this method uses the actual converter environment to investigate the implications of VTH shift and should therefore be of more interest to applications engineers as opposed to device physicists. Furthermore, a common problem is the underestimation of the VTH shift since recovery from charge detrapping can mask the true extent of the problem. The impact of temperature, the recovery time after stress removal, and polarity of the stress has been studied for a set of commercially available SiC MOSFET s.

/pdf/impact-of-bti-induced-threshold-voltage-shifts-in-shoot-2z0wyi86m6.pdf

Impact of BTI-Induced Threshold Voltage Shifts in Shoot-Through Currents From Crosstalk in SiC MOSFETs

The performance of SiC MOSFETs is limited by many defects at the SiC/SiO2 interface. However, there are no fully consistent atomic models of these defects or how their large densities arise. We show how the high heat of formation of SiO2 causes a selective oxidation of Si in SiC, leaving carbon clusters in SiO2. We consider chemical potentials across the interface from both the thermochemical and oxidation kinetics viewpoint. SiO2 native defects give states too far in energy from the SiC band edges, while defects in bulk SiC have too high a formation energy. Only carbon clusters have a low enough formation energy to give sufficient defect densities to account for the mobility loss, and experimental evidence for them is discussed.

Carbon cluster formation and mobility degradation in 4H-SiC MOSFETs

Junction temperature sensing is an integral part of both online and offline condition monitoring where direct access to the bare die surface is not available. Given a defined power input, the junction temperature enables the estimation of the junction-to-case thermal resistance, which is a key indicator of packaging failure mechanisms like solder voiding and cracks. The use of temperature sensitive electrical parameters (TSEPs) has widely been proposed as a means of junction temperature sensing; however, there are certain challenges regarding their use in SiC MOSFETs. Bias temperature instability (BTI) from charge trapping in the gate dielectric causes threshold voltage drift, which in SiC affects some of the key TSEPs including on -state resistance, body diode forward voltage as well as the current commutation rate. This article reviews the impact of BTI on the accurate junction temperature measurement using TSEPs in SiC MOSFETs.

/pdf/bias-temperature-instability-and-junction-temperature-5ah26l59e6.pdf

Bias Temperature Instability and Junction Temperature Measurement Using Electrical Parameters in SiC Power MOSFETs

Current generations of 4H-SiC metal-oxide-semiconductor field-effect transistors are still challenged by the high number of defects at the SiO2/SiC interface that limit both the performance and gate reliability of these devices. One potential source of the high density of interface defect states (D-it) is the stepped morphology on commonly used off-axially grown epitaxial surfaces, favoring incomplete oxidation and the formation of defective transition layers. Here we report measurements on intentionally modified 4H-SiC surfaces exhibiting both atomically flat and stepped regions where the generation of interface defects can be directly linked to differences in surface roughness. By combining spatially resolving structural, chemical, optical, and electrical analysis techniques, a strong increase of D-it for stepped surfaces was revealed while regions with an atomically flat SiC surface exhibited close-to-ideal interface properties.

/pdf/two-dimensional-defect-mapping-of-the-sio-2-4-h-sic-1q6iagu5ob.pdf

Two-dimensional defect mapping of the SiO 2 /4 H −SiC interface

High power SiC MOSFET technologies are critical for energy saving in, e.g., distribution of electrical power. They suffer, however, from low near-interface mobility, the origin of which has not yet been conclusively determined. Here, we present unique concerting evidence for the presence of interface defects in the form of carbon clusters at native thermally processed oxides of SiC. These clusters, with a diameter of 2–5 nm, are HF-etch resistant and possess a mixture of graphitic (sp2) and amorphous (sp3 mixed in sp2) carbon bonds different from the normal sp3 carbon present in 4H-SiC. The nucleation of such defects during thermal oxidation as well as their atomic structure is elucidated by state-of-the-art atomistic and electronic structure calculations. In addition, our property prediction techniques show the impact of the simulated carbon accumulates on the electronic structure at the interface.

/pdf/evidence-for-carbon-clusters-present-near-thermal-gate-4zw31hz2ow.pdf

Dipanwita Dutta

Papers

Two-dimensional defect mapping of the SiO 2 /4 H −SiC interface

Evidence for carbon clusters present near thermal gate oxides affecting the electronic band structure in SiC-MOSFET