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Two-dimensional defect mapping of the SiO 2 / 4 H –
SiC interface
Judith Woerle, Brett Johnson, Corrado Bongiorno, Kohei Yamasue, Gabriel
Ferro, Dipanwita Dutta, Thomas Jung, Hans Sigg, Yasuo Cho, Ulrike
Grossner, et al.
To cite this version:
Judith Woerle, Brett Johnson, Corrado Bongiorno, Kohei Yamasue, Gabriel Ferro, et al.. Two-
dimensional defect mapping of the SiO 2 / 4 H – SiC interface. Physical Review Materials, American
Physical Society, 2019, 3 (8), pp.084602. �10.1103/physrevmaterials.3.084602�. �hal-02322052�
PHYSICAL REVIEW MATERIALS 3, 084602 (2019)
Editors’ Suggestion
Two-dimensional defect mapping of the SiO
2
/4H-SiC interface
Judith Woerle ,
1,2,*
Brett C. Johnson,
3
Corrado Bongiorno,
4
Kohei Yamasue,
5
Gabriel Ferro,
6
Dipanwita Dutta,
1
Thomas A. Jung,
1
Hans Sigg,
1
Yasuo Cho,
5
Ulrike Grossner,
2
and Massimo Camarda
1,2
1
Paul Scherrer Institute, Forschungsstrasse 111, 5232 Villigen, Switzerland
2
Advanced Power Semiconductor Laboratory, ETH Zurich, Physikstrasse 3, 8092 Zurich, Switzerland
3
Centre for Quantum Computing and Communication Technology, School of Physics, University of Melbourne, Victoria 3010, Australia
4
Consiglio Nazionale delle Ricerche–Istituto per la Microelettronica e Microsistemi (CNR-IMM),
Strada VIII 5, Zona Industriale, 95121 Catania, Italy
5
Research Institute of Electrical Communication, Tohoku University, 2-1-1 Katahira, Aoba, Sendai 980-8577, Japan
6
Laboratoire des Multimatériaux et Interfaces (UMR 5615), Université de Lyon, Université Claude Bernard Lyon 1,
CNRS, 43 boulevard du 11 Novembre 1918, 69622 Villeurbanne, France
(Received 22 March 2019; revised manuscript received 14 June 2019; published 15 August 2019)
Current generations of 4H-SiC metal-oxide-semiconductor field-effect transistors are still challenged by the
high number of defects at the SiO
2
/SiC interface that limit both the performance and gate reliability of these
devices. One potential source of the high density of interface defect states (D
it
) is the stepped morphology
on commonly used off-axially grown epitaxial surfaces, favoring incomplete oxidation and the formation of
defective transition layers. Here we report measurements on intentionally modified 4H-SiC surfaces exhibiting
both atomically flat and stepped regions where the generation of interface defects can be directly linked to
differences in surface roughness. By combining spatially resolving structural, chemical, optical, and electrical
analysis techniques, a strong increase of D
it
for stepped surfaces was revealed while regions with an atomically
flat SiC surface exhibited close-to-ideal interface properties.
DOI: 10.1103/PhysRevMaterials.3.084602
I. INTRODUCTION
Silicon carbide (SiC), with its beneficial electrical and
thermal properties such as a wide band gap, high breakdown
field, high electron s aturation velocity, and high thermal con-
ductivity, is a very attractive material for a wide range of
high-power, high-voltage, and high-temperature applications.
Recently, SiC has also proved to be a promising quantum
technology platform and the first successful demonstrations
of it as a solid-state host material for single-photon sources or
quantum sensors have been reported [1–4].
Most of these applications require substrates with ho-
moepitaxial layers with a well-defined doping profile and
thickness to act as an active layer. In order to maintain the
polytype of the substrate during epitaxial growth, substrates
are cut a few degrees off-axis from the (0001) basal plane
(most common today are off-angles of 4
◦
toward the [11
¯
20]
direction), promoting a lateral epitaxial growth at the surface
steps [5,6].
While this step-controlled growth results in electronic-
grade single-polytype epilayers, it also leads to the creation
of atomic steps on the surface, commonly referred to as
microsteps [7], together with the formation of so-called iso-
lated macrosteps, consisting of bunched microsteps of several
nanometers in height [8].
Since the thermal oxidation process is strongly orientation-
dependent, the described surface morphology of 4H-SiC
*
woerle@aps.ee.ethz.ch
is expected to significantly influence the formation of the
SiO
2
/SiC interface. Apart from variations in the oxide growth
rate for different surface facets [9,10], a stepped surface may
lead to an increased number of interface defects as incomplete
crystal planes may favor nonideal oxidation with a larger
number of dangling bonds and the formation of a nonstoichio-
metric near-interface region [11,12]. This will not only affect
surface regions with a large number of isolated macrosteps,
but could also explain the high density of interface defect
states (D
it
) for all epitaxies grown under a small off-angle
which exhibit a continuous microstep pattern. The question of
whether macrosteps lead to performance limitations of metal-
oxide-semiconductor field-effect transistors (MOSFETs) due
to electric field crowding and higher surface roughness in
particular has been addressed previously but experimental
results are not conclusive [13–15]. While Liu et al. reported
that neither the channel mobility nor the density of interface
defects depended on the presence or absence of macrosteps,
Frazzetto et al. observed an improvement of channel mobility
and D
it
for samples with large macrosteps formed during
postimplantation annealing without a protective carbon cap.
Cabello et al. showed that the impact of surface roughness
scattering—the deflection of electrons by structural defects—
only starts to play a role for devices where the Coulomb
scattering due to interface defects in the channel region is low
enough and the quality of the interface is sufficiently high.
One reason for this wide spread of experimental results
may be related to the fact that all these studies use electrical
analysis methods such as capacitance-voltage (CV) or con-
ductance measurements which require large probing pads and
2475-9953/2019/3(8)/084602(8) 084602-1 ©2019 American Physical Society
JUDITH WOERLE et al. PHYSICAL REVIEW MATERIALS 3, 084602 (2019)
terrace
riser
micro-
steps
macrosteps
[0001]
[1120]
[1100]
[112x]
terrace
micro-
steps
FIG. 1. Schematic of an off-axis surface showing both micro-
and macrosteps as observed on commercial 4H-C epitaxial surfaces.
The subnanofacets at the riser exhibit different orientations com-
monly described with a Miller index of (11
¯
2x). The terrace along
the (0001) basal plane is atomically flat with only some sparsely
distributed single steps as indicated on the terrace on the right.
Note that the off-axis angle (the most common of these are 4
◦
)is
exaggerated in this sketch.
result in an averaged signal over a large number of micro-
or macrosteps. Hence, local variations in surface roughness
cannot be addressed with these techniques. In order to sep-
arate the contributions from different morphological features
to the formation of defects at the SiO
2
/SiC interface, spatially
resolving analysis techniques are required. Apart from their
small dimensions, isolated macrosteps present an ideal system
to explore the SiO
2
/SiC interface formed on SiC surfaces
with varying surface roughnesses as they are composed of two
different types of facets: atomically flat terraces [parallel to
the (0001) plane] and stepped risers [parallel to a (11
¯
2x) plane
with x = 25–30] [16–18]. A schematic plot of the faceted
morphology of an off-axis surface is depicted in Fig. 1.
In order increase the size and density of the macrosteps
and thus allow for the analysis of individual macrostep facets,
a high-temperature process can be employed, leading to a sur-
face reconstruction with an amplification of the macrosteps.
Here we use a so-called Si-melt process where the SiC surface
is capped with a Si piece during the high-temperature anneal-
ing [19,20]. While a noncapped annealing step often leads to
a carbon-rich surface, chemical analysis of Si-capped samples
confirmed a Si-rich surface reconstruction [21]. Using this
approach, macrosteps with heights of up to 200 nm and terrace
widths of several micrometers have been reported [20], an
order of magnitude larger than what is commonly observed for
surface reconstruction processes without any capping [22,23].
In this study, a variety of spatially resolved analysis tech-
niques are combined to form a comprehensive picture of the
morphology-dependent defect distribution at the SiO
2
/SiC in-
terface. For this purpose, the previously described Si-melt pro-
cess is performed prior to oxidation and the targeted, strongly
macrostepped surface with both atomically flat and stepped
facets is monitored by atomic-force microscopy (AFM). After
the thermal oxidation process, scanning transmission electron
microscopy (STEM) and electron energy loss spectroscopy
(EELS) provide structural and chemical information on the
transition region between the SiC bulk and the SiO
2
layer
on top. Finally, photoluminescence (PL) confocal microscopy
and local deep-level transient spectroscopy (local-DLTS) are
used to investigate the optical and electronic properties of
interface defects in a spatially resolved manner.
II. EXPERIMENTAL DETAILS
A. Sample preparation
For this study, 10 mm × 10 mm samples of a Wolfspeed
(0001) 4H-C wafer with a 4
◦
off-axis orientation towards the
11
¯
20 direction were used. The 15 μm thick n-type epitax-
ial layers had a nitrogen doping concentration of N
d
= 4 ×
10
15
cm
−3
. The samples exhibited a few isolated macrosteps
nonuniformly distributed along the [11
¯
20] direction with step
heights between 2 and 8 nm [10].
A strong and continuous macrostep formation was ob-
tained by a Si-melt process where a piece of Si was melted on
top of the 4H-C wafer [20]. After this process, the solidified
silicon was removed by etching the samples for several hours
in a solution of HF + HNO
3
. Subsequently, samples with
and without the described Si-melt process were thoroughly
cleaned and then thermally oxidized at 1050
◦
C for up to 24h
in an O
2
ambient, resulting in SiO
2
layers with thicknesses
up to 30 nm. No further postoxidation annealing steps were
applied.
TEM samples of the SiO
2
/SiC interface were prepared by
capping the oxide with a 500 nm thick Al layer before milling
the lamellas with a focused-ion beam first at 30 keV and 98 pA
and finally at 5 keV and 47 pA [24]. Subsequently, the samples
were cleaned and thinned further to around 80 nm using the
Fischione 1040 Nanomill TEM specimen preparation system.
The orientation of the lamellas was chosen to be orthogonal
to the s urface steps.
For the local-DLTS measurements, a 100 nm thick Ni layer
was deposited on the back of the sample to provide good
Ohmic contact. For electrical analysis via capacitance-voltage
measurements (see the Supplemental Material [46]), circular
Al contacts (r = 300 μm) were deposited on top of the SiO
2
and Ni was used for the Ohmic backside contact.
B. Sample characterization
AFM analysis was conducted with either a Bruker Multi-
Mode 8 AFM or a Bruker Dimension 3100 AFM in tapping
mode with a tapping frequency of 150 kHz. The probe tips had
radii down to 2 nm to enhance the lateral resolution. All AFM
maps shown here were performed prior to thermal oxidation.
The STEM analysis was performed with a JEOL
ARM200CF using an accelerating voltage of 60 keV and
a spot size of 0.13 nm. EELS spectra were collected with
a Gatan quantum spectrometer equipped with dual EELS
acquisition and fast shutter capabilities. Pixel sizes spanned
from 0.1 nm to 0.05 nm and the energy dispersion was fixed at
0.25 eV/pixel in order to have the silicon, carbon, and oxygen
signals in the same spectrum.
For optical characterization, a custom-built confocal mi-
croscope was used. It was equipped with a 532 nm continuous
wave laser, a dichroic mirror, a high-NA (0.95) 100× air
objective, a 560 nm long pass filter, and a fiber-coupled
single-photon counting module [see also Fig. 4(a)]. The
theoretical diffraction-limited spatial resolution was 280 nm
for emission wavelengths of 600 nm. The samples were
mounted onto a piezoelectric XYZ scanning stage allowing
for 100 μm × 100 μm scans. All confocal images presented
here were collected at room temperature. For the ensemble PL
084602-2
TWO-DIMENSIONAL DEFECT MAPPING OF THE … PHYSICAL REVIEW MATERIALS 3, 084602 (2019)
6 m
120 nm
6 nm-6 nm
(a)
(b)
7 nm-7 nm
6 m
(c)
150 nm-150 nm
0°-10°
30 nm-30 nm
(d)
0°-10°
300 nm
FIG. 2. (a) AFM images of an unprocessed (0001) 4H-C epitaxial surface showing a random distribution of isolated macrosteps. (b) Isolated
macrostep consisting of a double-peak with atomically flat terraces and a faceted riser in between. The phase image (bottom left) also shows
the microstepping of the surface away from the macrostep. (c) Surface morphology after the Si-melt process and subsequent Si removal. (d) A
zoom-in view of a macrostep in (c) showing two wide terraces separated by a riser facet composed of several smaller steps. The white stripe in
the phase map is a measurement artifact. Note that the scan sizes of (b) and (d) are different.
measurements, a micro-Raman Renishaw InVia spectrometer
equipped with a 532 nm laser with 1mW power was used. The
exposure time for all PL spectra was 50 s.
Local-DLTS measurements were performed using a com-
mercial contact-mode AFM (Bruker Icon) with a home-built
scanning nonlinear dielectric microscopy (SNDM) probe os-
cillating at a frequency of 1 GHz [see Fig. 6(a)][25,26]. The
radius of the Pt-coated probing tip forming a capacitor with
the SiO
2
/SiC stack was 150 nm and the scan size was 1 μm ×
1 μm. For the measurements, voltage pulses with amplitudes
between 0 and −5V and with a pulse width of t
pw
= 0.5 μs
were applied to the samples. The repetition frequency of
the pulses was 10 kHz. Assuming a capture cross section
of the interface traps of σ
S
= 4 × 10
−16
cm
2
(obtained from
standard-DLTS measurements), an energy depth of 0.38 eV
below the conduction band was probed.
III. RESULTS
A. AFM analysis
Before thermal oxidation, the surface topography of the
unannealed and annealed samples were studied by height and
phase AFM. While height maps image the surface topography,
phase maps are error images showing the phase difference be-
tween the oscillating cantilever and the drive signal. Although
a quantitative interpretation of the phase maps is difficult, they
often reveal additional properties of the sample material itself.
Figure 2 shows typical macrostep distributions for samples
before and after the Si capping and high-temperature an-
neal. As-grown Si-face 4H-C epitaxial layers exhibit isolated
macrosteps with heights of several nanometers which are
nonuniformly distributed across the surface [10,27,28], as
depicted in Fig. 2(a). Figure 2(b) shows a high-resolution
height (top right) and phase (bottom left) image of such an
isolated macrostep with its typical double-hill-valley structure
composed of two types of facets: atomically flat terraces
parallel to the (0001) plane and bunched risers parallel to a
(11
¯
2x) plane. The phase image also resolves the continuously
microstepped surface of standard epitaxial layers with step
heights of 2 to 4 bilayers (2.5–5 Å).
The macrosteps of the Si-melted sample in Fig. 2(c)
on the other hand have heights of up to a few hundred
nanometers and terrace widths in the micrometer range. Sim-
ilarly to the isolated macrosteps on the untreated surface,
they are composed of two types of facets: step-free terraces
and step-bunched risers, as depicted in Fig. 2(d). Here, the
risers are composed of an accumulation of steps, each of them
several nanometers high and exhibiting again a subnanometer
faceting. Additional 1D line scans of macrosteps as shown in
Figs. 2(b) and 2(d) are included in the Supplemental Material
[46].
For all further analysis presented in the subsequent sec-
tions, three different types of surface morphologies are distin-
guished: surfaces with a continuous nanofaceting (microsteps)
as observed on common, unmodified SiC epitaxial surfaces as
well as atomically flat terraces and strongly bunched risers of
macrostepped epitaxial surfaces after the Si-melt process.
B. STEM/EELS analysis
In EELS, a thin SiO
2
/SiC cross-section specimen is ex-
posed to an electron beam and the energy loss of the scattered
electrons passing through the sample is detected, yielding
information on the atoms the electrons interacted with. By
scanning across a larger 2D window and collecting an EELS
spectrum for each pixel, chemical composition maps across
the SiO
2
/SiC interface can be obtained.
For the EELS analysis, lamellas with all three distinct
SiC surface morphologies were prepared. In the case of the
macrostep terraces on the surface-modified sample [parallel
to the (0001) basal plane], a distinction between completely
step-free regions and regions with single steps, sporadically
present at such terraces, was made. All samples used for the
EELS analysis had the same oxide thickness of 30 nm.
Figure 3 shows the high-resolution dark-field (DF) cross-
section STEM images and corresponding EELS profiles for
different interface regions. For the EELS profiles, several rows
of the 2D scans parallel to the interface were averaged to
reduce the noise. For the interpretation of the profiles, an
approach similar to that suggested in Ref. [12] was followed
where the interface (at the origin of the x axis) is deter-
mined with the help of the dark-field image using the last
atomic SiC crystal plane. Three chemical components are
separately analyzed: apart from the carbon and oxygen maps,
084602-3
JUDITH WOERLE et al. PHYSICAL REVIEW MATERIALS 3, 084602 (2019)
FIG. 3. EELS profiles (left) with traces of carbon, oxygen, and
SiO
x
C
y
and corresponding dark-field STEM images (right) from
(a) an atomically flat region of a terrace, (b) a single step of a terrace,
(c) a nonmodified surface with microsteps, and (d) a step-bunched
macrostep riser. For the EELS line profiles, EELS spectra were
averaged over a 2 nm large area parallel to the interface. In (a), also a
reference SiO
x
C
y
profile of a deposited SiO
2
/SiC interface is shown
(shaded area) where no transition region is expected. In the case of
the atomically flat terrace, both the C signal and the SiO
x
C
y
spectrum
overlap perfectly with the reference sample.
substoichiometric SiO
x
C
y
(also including suboxides without
any C atoms, i.e., SiO
x
) from an energy window between
99 eV and 103 eV is extracted. By choosing this energy
range, fully oxidized Si
+4
atoms at energies above 104 eV
do not contribute to the EELS signal and the profile quickly
decreases in the SiO
2
bulk where all Si atoms are surrounded
by oxygen.
Flat terraces, depicted in Fig. 3(a), exhibit a complete last
SiC bilayer stacking without any observable steps in the DF
image and a very good overlap of the C and SiO
x
C
y
signals in
the EELS spectrum. Given the narrow width of the transition
region between SiC bulk and the SiO
2
of less than 2 nm
which is close to the sensitivity limit of this technique [29],
we consider this interface to be abrupt. Also shown in Fig. 3(a)
is the smoothened substoichiometric SiO
x
C
y
EELS profile of
aSiO
2
/SiC interface with a low-temperature deposited SiO
2
which was analyzed in parallel to the macrostepped samples.
The perfect overlap of the two SiO
x
C
y
spectra supports our
interpretation of an ideal SiO
2
/SiC interface on the atomically
flat terrace.
For a flat SiC terrace where a few single steps are present
[Fig. 3(b)], the drop of the SiO
x
C
y
signal moves away from the
interface, which is interpreted as an increased contribution of
an only partially oxidized SiC plane containing some residual
Si, C, and O bonds.
An increased SiO
x
C
y
signal is also observed for the
SiO
2
/SiC sample which did not undergo the Si-melt process
shown in Fig. 3(c). This trend is even more pronounced in the
case of the strongly stepped riser facet as depicted in Fig. 3(d).
Here, the SiO
x
C
y
signal extends more than 1 nm into the SiO
2
bulk, suggesting an increased thickness of the transition
layer and a larger contribution of a substoichiometric SiO
x
C
y
region.
For some of the EELS profiles which were acquired either
on micro- or macrostepped SiC surface regions, we did ob-
serve a slightly increased carbon signal, appearing as a small
peak at 0.2 nm away from the interface in the SiO
2
bulk (not
shown here; see the Supplemental Material [46]).
C. PL analysis
In order to correlate the observed thickness variations of
the transition region with the density of interface defects, a
mapping of the SiO
2
/SiC interface was performed using con-
focal PL measurements. Figures 4(b) and 4(d) depict reflectiv-
ity measurements of the SiO
2
/SiC interface on samples with
and without a previously employed Si-melt process where
the height profile of the inspected regions is clearly visible.
Confocal images of the same regions [Figs. 4(d) and 4(e)]
show the drastic difference in emission signal for the differ-
ent surface morphologies: While the atomically flat terraces
exhibit a defect density of approximately 0.62 emitters/μm
2
with an average defect emission count rate of 128 kilocounts
per second at an excitation power of 1 mW, a much higher
density of defects is observed as bright vertical lines along the
1
¯
100 direction at the stepped risers. A slightly higher density
of defects (1 emitter/μm
2
) but an emission intensity similar to
that for the terraces is found for nonmodified surface regions.
An increased number of defect centers is also observed close
to areas with crystal defects or damage (e.g., scratches) of the
epitaxial layer (not shown here).
The corresponding room temperature ensemble PL spectra,
measured with a laser spot size of 2 μm, are presented in
Fig. 5. Single interface defects exhibit a noticeable spectral
variability, leading to a broad peak centered around 750 nm.
Compared to a nonmodified surface, the photoluminescence
slightly decreases for areas on the macrosteps terrace, while it
is considerably higher for the riser. This is in accordance with
conductance measurements reported previously [21] and with
084602-4
![FIG. 6. (a) Schematic of the local-DLTS setup, adapted from [25]. (b) Dit map for a sample with enhanced macrosteps. The oxide thickness on terraces and risers was estimated to be 7 nm and 11 nm, respectively. (c) Dit map for an unmodified SiC surface with 8 nm thermally grown SiO2 on top. For both Dit maps, Eit = 0.38 eV.](/figures/fig-6-a-schematic-of-the-local-dlts-setup-adapted-from-25-b-mngpkjtj.webp)
