An untethered, entirely soft robot is designed to operate autonomously by combining microfluidic logic and hydrogen peroxide as an on-board fuel supply. Soft robotics have so far necessarily included some 'hard' or metallic elements, in particular in the form of batteries or wiring, to connect them to an external power source. Additionally, external wiring tethering them to a power source places limits on the autonomy of such robots. Now Jennifer Lewis and colleagues have combined a 3D-printed soft polymeric robot with microfluidic logic and hydrogen peroxide as an onboard fuel to produce an eight-armed robot — an 'octobot' — that actuates its arms, without the incorporation of any hard structures. The hydrogen peroxide decomposes in the presence of a platinum catalyst to produce oxygen and a volumetric expansion that fills bladders embedded within the arms of the octobot. The design of the fuel reservoirs, microfluidic channels and vents to release the gas means that two sets of arms actuate cyclically. Soft robots possess many attributes that are difficult, if not impossible, to achieve with conventional robots composed of rigid materials1,2. Yet, despite recent advances, soft robots must still be tethered to hard robotic control systems and power sources3,4,5,6,7,8,9,10. New strategies for creating completely soft robots, including soft analogues of these crucial components, are needed to realize their full potential. Here we report the untethered operation of a robot composed solely of soft materials. The robot is controlled with microfluidic logic11 that autonomously regulates fluid flow and, hence, catalytic decomposition of an on-board monopropellant fuel supply. Gas generated from the fuel decomposition inflates fluidic networks downstream of the reaction sites, resulting in actuation12. The body and microfluidic logic of the robot are fabricated using moulding and soft lithography, respectively, and the pneumatic actuator networks, on-board fuel reservoirs and catalytic reaction chambers needed for movement are patterned within the body via a multi-material, embedded 3D printing technique13,14. The fluidic and elastomeric architectures required for function span several orders of magnitude from the microscale to the macroscale. Our integrated design and rapid fabrication approach enables the programmable assembly of multiple materials within this architecture, laying the foundation for completely soft, autonomous robots.

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An integrated design and fabrication strategy for entirely soft, autonomous robots

In the last two decades, the vast majority of microfluidic systems have been built in poly(dimethylsiloxane) (PDMS) by soft lithography, a technique based on PDMS micromolding. A long list of key PDMS properties have contributed to the success of soft lithography: PDMS is biocompatible, elastomeric, transparent, gas-permeable, water-impermeable, fairly inexpensive, copyright-free, and rapidly prototyped with high precision using simple procedures. However, the fabrication process typically involves substantial human labor, which tends to make PDMS devices difficult to disseminate outside of research labs, and the layered molding limits the 3D complexity of the devices that can be produced. 3D-printing has recently attracted attention as a way to fabricate microfluidic systems due to its automated, assembly-free 3D fabrication, rapidly decreasing costs, and fast-improving resolution and throughput. Resins with properties approaching those of PDMS are being developed. Here we review past and recent efforts in 3D-printing of microfluidic systems. We compare the salient features of PDMS molding with those of 3D-printing and we give an overview of the critical barriers that have prevented the adoption of 3D-printing by microfluidic developers, namely resolution, throughput, and resin biocompatibility. We also evaluate the various forces that are persuading researchers to abandon PDMS molding in favor of 3D-printing in growing numbers.

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The upcoming 3D-printing revolution in microfluidics

The advent of soft lithography allowed for an unprecedented expansion in the field of microfluidics. However, the vast majority of PDMS microfluidic devices are still made with extensive manual labor, are tethered to bulky control systems, and have cumbersome user interfaces, which all render commercialization difficult. On the other hand, 3D printing has begun to embrace the range of sizes and materials that appeal to the developers of microfluidic devices. Prior to fabrication, a design is digitally built as a detailed 3D CAD file. The design can be assembled in modules by remotely collaborating teams, and its mechanical and fluidic behavior can be simulated using finite-element modeling. As structures are created by adding materials without the need for etching or dissolution, processing is environmentally friendly and economically efficient. We predict that in the next few years, 3D printing will replace most PDMS and plastic molding techniques in academia.

3D-Printed Microfluidics.

The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Integrated circuit I/O using a high performance bus interface

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations.
We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space.
Our DPGA, a fine-grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite-state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds.
Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20$\times$ the computational density of conventional processors.
Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

Reconfigurable Architectures for General-Purpose Computing

A microfluidic valve that amplifies the pressure in a fluid channel enables the realization of static microfluidic digital control logic. This in turn could enable more versatility and integration in the control of flows in ‘lab-on-a-chip’ systems.

Static control logic for microfluidic devices using pressure-gain valves

MIPS-X is a 32-b RISC microprocessor implemented in a conservative 2-/spl mu/m, two-level-metal, n-well CMOS technology. High performance is achieved by using a nonoverlapping two-phase 20-MHz clock and executing one instruction every cycle. To reduce its memory bandwidth requirements, MIPS-X includes a 2-kbyte on-chip instruction cache. The authors provide an overview of MIPS-X, focusing on the techniques used to reduce the complexity of the processor and implement the on-chip instruction cache.

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MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache

A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.

Memory module with offset data lines and bit line swizzle configuration

Analysis of power distribution in VLSI circuits requires the solution of a large network of resistors and current sources. Fortunately, these resistor networks have certain characteristic properties that permit partitioning into smaller, easier to solve sections. The authors present a set of techniques that can be used to identify and quickly solve three characteristic network configurations: trees, simple loops, and series resistors with interspersed current sources. Methods for efficiently solving other sections of the network are also explored. System performance of several designs is reported. >

Techniques for calculating currents and voltages in VLSI power supply networks

This paper has described the different trends in the digital circuit design and changes over the past two decades moving from chips that contained tens of thousands of devices to today' s chips that may contain over a billion transistors. The job of the digital circuit designer has grown with the chips, moving from optimizing and validating gates, to working on functional units, to now designing complete systems. While the progress in digital design has clearly been tremendous, power challenges are an important issue in future VLSI designing system. Designers used considerable ingenuity to make CMOS compatible with the older bipolar ECL/TTL families, concentrating on meeting all aspects of the without requiring external components.

Don Stark

Papers

Static control logic for microfluidic devices using pressure-gain valves

MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache

Memory module with offset data lines and bit line swizzle configuration

Techniques for calculating currents and voltages in VLSI power supply networks

Digital Circuit Design Trends